Intel DMA Coalescing White Paper

occurs in bursts, leaving long periods
of inactivity. IEEE 802.3az enables the
network interface to enter into a Low-
Power-Idle (LPI) mode when the adapter
detects that the network link is not being
fully used. This enables link partners to
save energy by cycling between active
and LPI states.
Operation at Maximum Efficiency
Intel’s PMT provides a new mode of
operation called “DMA Coalescing.” It
changes the system behavior of the LAN
interface by changing how frequently
packet data is delivered to the system by
batching the delivery of packet data and
device interrupts to the chipset, CPU and
memory.
This behavior has the following effects:
• By batching and increasing the amount
of data transferred during any given
time to the system, the LAN device
enables the rest of the system to enter
into low-power platform states, that is
PCIe enters ASPM L1, the CPUs activate
Package Cx states, and main-memory
goes into self-refresh. DMA coalescing
enables these components to stay in
these low-power platform states for
longer periods.
• Intel’s PMT attempts to make the DMA
frequency predictable. This predictability
enables the host CPU to pick a deeper
low-power state than it might otherwise
choose.
• When the CPU wakes to process network
activity, the operating system is able
to run at higher efciency because
software has more “work” to do for any
given interrupt. The observable effect,
with benchmarks, is, with increasing
network I/O block sizes, CPU usage drops
and I/O bandwidth increases.
Figure 1 shows that without DMA
Coalescing the platform is typically kept
in higher power states. The vertical
lines show the random nature of
platform interrupts. Power consumption,
represented by the top line, is higher
overall because the processor, memory
and other system components are
brought out of lower power states to
handle the incoming data.
In addition, system components are not
allowed enough time to achieve deeper
low-power states.
Figure 2 shows that, with DMA Coalescing,
the incoming data packets and interrupts
associated with these DMA calls are
intelligently batched to keep the system
devices in lower power states. This
enables the system to handle the packets
and interrupts more efciently. The
technique also gives system components
the opportunity to achieve deeper low
power states.
Table of Contents
Introduction                      1
Power Management Technology    1
Additional Congifuration Info      4
Controlling DMA Coalescing        5
Verifying Behavior                5
References                       6
Figure 1 Figure 2
2
Intel® I350 Ethernet Controller & DMA Coalescing