Intel® Celeron® Processor 400Δ Series Datasheet — Supporting the Intel® Celeron® processor 420Δ, 430Δ, 440Δ, and 450Δ August 2008 Document Number: 316963-002
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Packaging Terminology ............................................................. 10 1.2 References .......................................................................................................
5.3 5.4 5.2.2 Thermal Monitor 2 ..................................................................................79 5.2.3 On-Demand Mode ...................................................................................80 5.2.4 PROCHOT# Signal ..................................................................................81 5.2.5 THERMTRIP# Signal ................................................................................81 Thermal Diode............................................................
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 VCC Static and Transient Tolerance ............................................................................. 21 VCC Overshoot Example Waveform ............................................................................. 22 Differential Clock Waveform ...................................................................................... 30 Differential Clock Crosspoint Specification .............................
21 22 23 24 25 26 27 28 29 30 31 32 33 6 Package Handling Guidelines......................................................................................39 Processor Materials ...................................................................................................40 Alphabetical Land Assignments...................................................................................46 Numerical Land Assignment .......................................................................................
Revision History Revision Number -001 -002 Description • Initial release • ® Added Intel Date June 2007 Celeron ® processor 450 August 2008 § Datasheet 7
Intel® Celeron® Processor 400 Series Features • Available at 1.60 GHz, 1.8 GHz, 2.00 GHz, 2.
Introduction 1 Introduction The Intel® Celeron® processor 400 series is a desktop processor that combines the performance of the previous generation of Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. Intel Celeron Processor 400 is a 64-bit processor that maintain compatibility with IA-32 software.
Introduction 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: • Intel Celeron Processor 400 Series — Single core processor in the FC-LGA6 package with a 1 MB or 512 KB L2 cache. • Processor — For this document, the term processor is the generic form of the Intel Celeron processor 400 series. The processor is a single package that contains one exectution unit. • Keep-out zone — The area on or near the processor that system design can not use.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document Location Intel® Celeron® Processor 400 Series Specification Update www.intel.com/ design/processor/ specupdt/316964.htm Intel® Celeron® Processor 400 Series Thermal and Mechanical Design Guidelines www.intel.com/ design/processor/ designex/316965.
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2. Voltage Identification Definition VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VCC_MAX VID 6 VID 5 VID 4 VID 3 VID 2 VID 1 VCC_MAX 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.8750 0 1 1 1 0 0 1.2625 1 1 1 0 1 0 0.8875 0 1 1 0 1 1 1.2750 1 1 1 0 0 1 0.9000 0 1 1 0 1 0 1.2875 1 1 1 0 0 0 0.9125 0 1 1 0 0 1 1.3000 1 1 0 1 1 1 0.
Electrical Specifications 2.4 Market Segment Identification (MSID) The MSID[1:0] signals may be used as outputs to determine the Market Segment of the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP. Table 3.
Electrical Specifications The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.
Electrical Specifications Table 4. Absolute Maximum and Minimum Ratings Symbol Notes1, 2 Parameter Min Max Unit VCC Core voltage with respect to VSS –0.3 1.55 V - VTT FSB termination voltage with respect to VSS –0.3 1.55 V - TC Processor case temperature See Chapter 5 See Chapter 5 °C - TSTORAGE Processor storage temperature –40 85 °C 3, 4, 5 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.
Electrical Specifications 2.6.2 DC Voltage and Current Specification Table 5. Voltage and Current Specifications Symbol Parameter VID Range VID Processor Number VCC 2.2 GHz 440 2.0 GHz 430 1.8 GHz 420 1.6 GHz VCC_BOOT Default VCC voltage for initial power up VCCPLL PLL VCC ICC ITT Unit 1.0000 — 1.3375 V 3 Refer to Table 6 and Figure 1 V 4, 5, 6 V — 1.10 — - 5% 1.50 + 5% — — 450 2.2 GHz 440 2.0 GHz 430 1.8 GHz 35 420 1.
Electrical Specifications 8. 9. 10. 11. 12. Table 6. VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land. Baseboard bandwidth is limited to 20 MHz. This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.
Electrical Specifications Figure 1. VCC Static and Transient Tolerance Icc [A] 0 10 20 30 VID - 0.000 VID - 0.013 Vcc Maximum VID - 0.025 VID - 0.038 VID - 0.050 Vcc [V] VID - 0.063 Vcc Typical VID - 0.075 VID - 0.088 Vcc Minimum VID - 0.100 VID - 0.113 VID - 0.125 VID - 0.138 VID - 0.150 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2. This loadline specification shows the deviation from the VID set point.
Electrical Specifications Figure 2. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.6.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 7 when measured across the VCC_SENSE and VSS_SENSE lands.
Electrical Specifications 2.7.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications Table 8. FSB Signal Groups (Sheet 2 of 2) Signal Group Signals1 Type VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI Power/Other NOTES: 1. Refer to Section 4.2 for signal descriptions. 2.
Electrical Specifications 2.7.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs for the processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 2.7.
Electrical Specifications . Table 13. CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage -0.10 VTT * 0.30 V 2, 3 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 4, 5, 3 VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 6, 5, 3 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.
Electrical Specifications 2.7.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 9 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications for both 50 Ohm and 60 Ohm platforms.
Electrical Specifications 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 15 for the processor supported ratios.
Electrical Specifications 2.8.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
Electrical Specifications 2.8.4 BCLK[1:0] Specifications (CK505 based Platforms) Table 17. Front Side Bus Differential BCLK Specifications Symbol Parameter VL Input Low Voltage VH Input High Voltage VCROSS(abs) Figure 3. Figure Notes1 -0.30 N/A N/A V 3 4 N/A N/A 1.15 V 3 4 0.300 N/A 0.550 V 3, 4 2,4,6 N/A N/A 0.140 V 3, 4 - N/A N/A 1.4 V 3 5 VUS Undershoot -0.300 N/A N/A V 3 5 Differential Output Swing 0.
Electrical Specifications Figure 4. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 250 + 0.5 (VHavg - 700) 350 300 250 250 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 5. Differential Measurements Slew_ris e Slew _fall +150 mV 0.0 V -150 mV +150 mV V_swing 0.
Electrical Specifications 2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) Table 18. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.150 0.00 0 N/A V 3 - VH Input High Voltage 0.660 0.70 0 0.850 V 3 - VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 3, 4 2, 8 VCROSS(rel) Relative Crossing Point 0.250 + 0.5(VHavg – 0.700) N/A 0.550 + 0.5(VHavg – 0.
Electrical Specifications Figure 6. Differential Clock Waveform Tph Overshoot BCLK1 VH Rising Edge Ringback V CROSS (ABS) Threshold Region V CROSS (ABS) Ringback Margin Falling Edge Ringback BCLK0 VL Undershoot Tpl Tp Tp = T1: BCLK[1:0] period T2: BCLK[1:0] period stability (not shown) Tph = T3: BCLK[1:0] pulse high time Tpl = T4: BCLK[1:0] pulse low time T5: BCLK[1:0] rise time through the threshold region T6: BCLK[1:0] fall time through the threshold region Figure 7.
Electrical Specifications 2.9 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die.
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 9.
Package Mechanical Specifications Figure 10.
Package Mechanical Specifications Figure 11.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 9 and Figure 10 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 13 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 13.
Package Mechanical Specifications 42 Datasheet
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 14 and Figure 15. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 14.
Land Listing and Signal Descriptions Figure 15.
Land Listing and Signal Descriptions Table 23. 46 Alphabetical Land Assignments Table 23.
Land Listing and Signal Descriptions Table 23. Datasheet Alphabetical Land Assignments Table 23.
Land Listing and Signal Descriptions Table 23. 48 Alphabetical Land Assignments Land Name Land # Signal Buffer Type FC37 AB3 FC38 FC39 Table 23.
Land Listing and Signal Descriptions Table 23. Datasheet Alphabetical Land Assignments Land Name Land # Signal Buffer Type VCC AC24 VCC VCC Table 23.
Land Listing and Signal Descriptions Table 23. 50 Alphabetical Land Assignments Land Name Land # Signal Buffer Type VCC AJ9 VCC VCC Table 23.
Land Listing and Signal Descriptions Table 23. Datasheet Alphabetical Land Assignments Land Name Land # Signal Buffer Type VCC K27 VCC VCC Table 23.
Land Listing and Signal Descriptions Table 23. 52 Alphabetical Land Assignments Land Name Land # Signal Buffer Type VSS A18 VSS VSS VSS VSS Table 23.
Land Listing and Signal Descriptions Table 23. Datasheet Alphabetical Land Assignments Land Name Land # Signal Buffer Type VSS AH7 VSS VSS Table 23.
Land Listing and Signal Descriptions Table 23. 54 Alphabetical Land Assignments Land Name Land # Signal Buffer Type VSS D24 VSS VSS Table 23.
Land Listing and Signal Descriptions Table 23. Datasheet Alphabetical Land Assignments Land Name Land # Signal Buffer Type VSS R27 VSS VSS VSS VSS Table 23.
Land Listing and Signal Descriptions Table 24. 56 Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type C22 VSS C23 C24 Table 24.
Land Listing and Signal Descriptions Table 24. Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. 60 Numerical Land Assignment Land # Land Name Signal Buffer Type N7 VSS Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type V7 VSS Table 24.
Land Listing and Signal Descriptions Table 24. 62 Numerical Land Assignment Land # Land Name Signal Buffer Type AC7 VSS Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AF25 VSS AF26 AF27 Table 24.
Land Listing and Signal Descriptions Table 24. 64 Numerical Land Assignment Land # Land Name Signal Buffer Type AJ15 VCC AJ16 AJ17 Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 25. Signal Description ( (Sheet 1 of 9)) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 25. Signal Description ( (Sheet 2 of 9)) Name Type Description BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[5:0]# Input/ Output BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
Land Listing and Signal Descriptions Table 25. Signal Description ( (Sheet 3 of 9)) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 25. Signal Description ( (Sheet 4 of 9)) Name DEFER# DRDY# Type Description Input DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 25. Signal Description ( (Sheet 5 of 9)) Name HIT# HITM# IERR# Type Input/ Output Input/ Output Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Land Listing and Signal Descriptions Table 25. Signal Description ( (Sheet 6 of 9)) Name Type Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. LOCK# Input/ Output PECI Input/ Output PECI is a proprietary one-wire bus interface. See Section 5.
Land Listing and Signal Descriptions Table 25. Signal Description ( (Sheet 7 of 9)) Name Type Description RS[2:0]# Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents. SKTOCC# Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present.
Land Listing and Signal Descriptions Table 25. Signal Description ( (Sheet 8 of 9)) Name THERMTRIP# Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 25. Signal Description ( (Sheet 9 of 9)) Name Type Description VRDSEL Input This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to VSS. VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane. VSSA Input VSSA is the isolated ground for internal PLLs.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to Section 5.2.
Thermal Specifications and Design Considerations Table 27. Figure 16. Thermal Profile Power (W) Maximum Tc (°C) Power Maximum Tc (°C) 0 43.2 20 53.0 2 44.2 22 54.0 4 45.2 24 55.0 6 46.1 26 55.9 8 47.1 28 56.9 10 48.1 30 57.9 12 49.1 32 58.9 14 50.1 34 59.9 16 51.0 35 60.4 18 52.0 Thermal Profile 65.0 60.0 55.0 Tcase (C) 50.0 45.0 40.0 35.0 30.0 0 y = 0.49x + 43.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 17 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel® Celeron® Processor 400 Series Thermal and Mechanical Design Guidelines. Figure 17.
Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations Figure 18. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VID VIDTM2 VID PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.3 Thermal Diode The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its collector shorted to ground. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control. Table 28, Table 29, and Table 30 provide the "diode" parameter and interface specifications.
Thermal Specifications and Design Considerations Table 29. Thermal “Diode” Parameters using Transistor Model Symbol Parameter IFW Forward Bias Current IE Emitter Current nQ Transistor Ideality Beta RT Series Resistance Min Typ Max Unit Notes 5 — 200 µA 1, 2 - 3, 4, 5 5 — 200 0.997 1.001 1.005 0.391 — 0.760 2.79 4.52 6.24 3, 4 Ω 3, 6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 28. 3.
Thermal Specifications and Design Considerations 5.4 Platform Environment Control Interface (PECI) 5.4.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 19 shows an example of the PECI topology in a system. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.
Thermal Specifications and Design Considerations . Figure 20. Conceptual Fan Control on PECI-Based Platforms TCONTROL Setting TCC Activation Temperature PECI = 0 Max Fan Speed (RPM) PECI = -10 Min PECI = -20 Temperature Note: Not intended to depict actual implementation . Figure 21.
Thermal Specifications and Design Considerations 5.4.2 PECI Specifications 5.4.2.1 PECI Device Address The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification. 5.4.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes. 5.4.2.
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 32. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 22. Processor Low Power State Machine 6.2.1 Normal State This is the normal operating state for the processor. 6.2.2 HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. The Extended HALT state is a lower power state as compared to the Stop Grant State.
Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
Features 6.2.4 HALT Snoop State and Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB).
Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 23 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 25. Space Requirements for the Boxed Processor (Top View) NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 26.
Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Intel® Celeron® Processor 400 Series Thermal and Mechanical Design Guidelines for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications Figure 28. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] B C Boxed Proc PwrHeaderPlacement 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 29. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top 1 view) Figure 30.
Boxed Processor Specifications 7.3.2 Variable Speed Fan The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum.
Boxed Processor Specifications §§ 98 Datasheet
Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Debug Tools Specifications 100 Datasheet
