Datasheet

Land Listing and Signal Descriptions
76 Datasheet
MSID[1:0] Input
MSID[1:0] (input) MSID0 is used to indicate to the processor
whether the platform supports 775_VR_CONFIG_05B processors. A
775_VR_CONFIG_05B processor will only boot if its MSID0 pin is
electrically low. A 775_VR_CONFIG_05A processor will ignore this
input.
MSID1 must be electrically low for the processor to boot.
PROCHOT#
Output
or
Input/
Output
For the processor, PROCHOT# can be configured via BIOS as an
output or a bi-directional signal.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that one or both
cores has reached its maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit (TCC) has been
activated, if enabled.
As a bi-directional signal, assertion of PROCHOT# by the system will
activate the TCC, if enabled, for both cores. The TCC will remain
active until the system de-asserts PROCHOT#. See Section 5.2.3 for
more details.
PWRGOOD Input
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then
transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable
before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins/
lands of all processor FSB agents. They are asserted by the current
bus owner to define the currently active transaction type. These
signals are source synchronous to ADSTB0#. Refer to the AP[1:0]#
signal description for a details on parity checking of these signals.
RESET# Input
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least one millisecond after V
CC
and BCLK have reached their proper
specifications. On observing active RESET#, all FSB agents will de-
assert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These
configuration options are described in the Section 6.1.
This signal does not have on-die termination and must be
terminated on the system board.
RS[2:0]# Input
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins/lands of all processor FSB
agents.
Table 25. Signal Description (Sheet 1 of 9)
Name Type Description