Datasheet

Datasheet 29

Electrical Specifications

2.7 Clock Specifications

2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the Celeron D processor core

frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier

will be set at its default ratio during manufacturing. Refer to Table 17 for the Celeron D

processor supported ratios.

The Celeron D processor uses a differential clocking implementation. For more

information on the Celeron D processor clocking, contact your Intel field

representative.

Table 17. Core Frequency to FSB Multiplier Configuration

Multiplication of System

Core Frequency to FSB

Frequency

Core Frequency

(133 MHz BCLK/

533 MHz FSB)

Notes

1, 2

NOTES:

1. Individual processors operate only at or below the rated frequency.

2. Listed frequencies are not necessarily committed production frequencies.

1/12 1.6 GHz -

1/13 1.8 GHz -

1/14 1.9 GHz -

1/15 2 GHz -

1/16 2.1 GHz -

1/17 2.3 GHz -

1/18 2.4 GHz -

1/19 2.5 GHz -

1/20 2.7 GHz -

1/21 2.8 GHz -

1/22 2.9 GHz -

1/23 3 GHz -

1/24 3.2 GHz -

1/25 3.3 GHz -