Datasheet

30 Datasheet
Electrical Specifications
NOTES:
1. V
OS
is measured overshoot voltage.
2. T
OS
is measured time duration above VID.
2.12.1 Die Voltage Validation
Overshoot events from application testing on real processors must meet the specifications in
Table 2-17 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that
are < 10 ns in duration may be ignored. These measurements of processor die level overshoot
should be taken with a 100 MHz bandwidth limited oscilloscope. Refer to the Voltage Regulator
Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket for additional voltage regulator
validation details.
2.13 GTL+ FSB Specifications
Termination resistors are not required for most GTL+ signals, as these are integrated into the
processor silicon.Valid high and low levels are determined by the input buffers which compare a
signal’s voltage with a reference voltage called GTLREF. Table 2-18 lists the GTLREF
specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board
using high precision voltage divider circuits.
Figure 2-4. V
CC
Overshoot Example Waveform
Time
Example Overshoot Waveform
Voltage (V)
VID
VID + 0.050
T
OS
V
OS
T
OS
: Overshoot time above VID
V
OS
: Overshoot above VID