Datasheet

Datasheet 3
Contents
Contents
1 Introduction....................................................................................................................................9
1.1 Terminology ........................................................................................................................10
1.1.1 Processor Packaging Terminology ........................................................................10
1.2 References .........................................................................................................................11
2 Electrical Specifications .............................................................................................................13
2.1 FSB and GTLREF...............................................................................................................13
2.2 Power and Ground Lands...................................................................................................13
2.3 Decoupling Guidelines........................................................................................................13
2.3.1 VCC Decoupling ....................................................................................................14
2.3.2 FSB GTL+ Decoupling...........................................................................................14
2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................14
2.4 Voltage Identification ..........................................................................................................15
2.4.1 Phase Lock Loop (PLL) Power and Filter ..............................................................17
2.5 Reserved, Unused, FC and TESTHI Signals......................................................................18
2.6 FSB Signal Groups .............................................................................................................19
2.7 GTL+ Asynchronous Signals ..............................................................................................20
2.8 Test Access Port (TAP) Connection ...................................................................................21
2.9 FSB Frequency Select Signals (BSEL[2:0]) .......................................................................21
2.10 Absolute Maximum and Minimum Ratings .........................................................................22
2.11 Processor DC Specifications ..............................................................................................22
2.12 VCC Overshoot Specification .............................................................................................29
2.12.1 Die Voltage Validation ...........................................................................................30
2.13 GTL+ FSB Specifications....................................................................................................30
3 Package Mechanical Specifications ..........................................................................................33
3.1 Package Mechanical Specifications ...................................................................................33
3.1.1 Package Mechanical Drawing ...............................................................................33
3.1.2 Processor Component Keep-Out Zones................................................................37
3.1.3 Package Loading Specifications............................................................................37
3.1.4 Package Handling Guidelines................................................................................37
3.1.5 Package Insertion Specifications...........................................................................38
3.1.6 Processor Mass Specification................................................................................38
3.1.7 Processor Materials ...............................................................................................38
3.1.8 Processor Markings ...............................................................................................38
3.1.9 Processor Land Coordinates .................................................................................39
4 Land Listing and Signal Descriptions .......................................................................................41
4.1 Processor Land Assignments .............................................................................................41
4.2 Alphabetical Signals Reference..........................................................................................64
5 Thermal Specifications and Design Considerations................................................................73
5.1 Processor Thermal Specifications ......................................................................................73
5.1.1 Thermal Specifications ..........................................................................................73
5.1.2 Thermal Metrology.................................................................................................77
5.2 Processor Thermal Features ..............................................................................................77
5.2.1 Thermal Monitor.....................................................................................................77