Intel® Pentium® D Processor 800Δ Sequence Datasheet – On 90 nm Process in the 775-land LGA Package and supporting Intel® Extended Memory 64 TechnologyΦ February 2006 Document Number: 307506-003
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Contents Contents 1 Introduction.................................................................................................................................... 11 1.1 1.2 2 Electrical Specifications ................................................................................................................. 15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 Package Mechanical Drawing ............................................................................................
Contents 5.2 6 Features ........................................................................................................................................ 85 6.1 6.2 7 7.2 7.3 8.2 8.3 Mechanical Specifications .................................................................................................. 98 8.1.1 Cooling Solution Dimensions................................................................................. 98 8.1.2 Boxed Processor Fan Heatsink Weight ...........................
Contents Figures 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 5-1 5-2 5-3 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 8-1 8-2 8-3 8-4 8-5 8-6 VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor............ 22 VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor............ 24 VCC Overshoot Example Waveform .......................................................................................... 25 Phase Lock Loop (PLL) Filter Requirements...............
Contents Tables 1-1 References ................................................................................................................................. 13 2-1 Voltage Identification Definition .................................................................................................. 17 2-2 Processor DC Absolute Maximum Ratings ................................................................................ 19 2-3 Voltage and Current Specifications ..........................................
Contents Revision History Revision Number Description Date -001 • Initial release May 2005 -002 • Added Balanced Technology Extended (BTX) Type I Boxed Processor Specifications chapter. October 2005 -003 • Added Intel® Pentium® D processor 805 specifications. • Updated THERMTRIP# signal description in Table 4-3.
Contents 8 Datasheet
Contents Intel® Pentium® D Processor 800 Sequence Features • Available at 3.20 GHz, 3 GHz, 2.80 GHz, and • Optimized for 32-bit applications running on 2.
Contents 10 Datasheet
Introduction 1 Introduction The Intel® Pentium® D processor extends Intel's Desktop dual-core product line. The Pentium D processor uses Flip-Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775land LGA socket, referred to as the LGA775 socket. The Pentium D processor, like the Intel® Pentium 4 processor in the 775-land package, utilizes the Intel NetBurst® microarchitecture and maintains the tradition of compatibility with IA-32 software.
Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: Table 1-1. References Document Document Location Intel® D Processor and Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines http://developer.intel.com/design/ pentiumXE/designex/306830.htm Intel® Pentium® Processor Extreme Edition and Intel® Pentium® D Processor Specification Update http://developer.intel.com/design/ PentiumXE/specupdt/ 306832.
Introduction 14 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The Intel® Pentium® D processor has 226 VCC (power) and 273 VSS (ground) inputs for on-chip power distribution. All VCC lands must be connected to the processor power plane, while all VSS lands must be connected to the system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The Pentium D processor package integrates signal termination on the die as well as incorporates high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system baseboard for proper GTL+ bus operation. 2.3 Voltage Identification The Voltage Identification (VID) specification for the Pentium D processor is defined by the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket.
Electrical Specifications Table 2-1. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.
Electrical Specifications 2.4 Reserved, Unused, FC and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications 2.5 Voltage and Current Specifications 2.5.1 Absolute Maximum and Minimum Ratings Table 2-2 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications Table 2-3. Voltage and Current Specifications Symbol VID range Processor number Parameter Min Typ Max Unit Notes VID 1.200 — 1.400 V 1 Refer to Table 2-5 and Figure 2-2 V 2, 3, 4, 5 Refer to Table 2-4 and Figure 2-1 V 2, 3, 5, 6, 7 A 8 Core Frequency VCC for 775_VR_CONFIG_05B processor (PRB = 1) VCC 840 3.20 GHz 830 3 GHz VCC for 775_VR_CONFIG_05A processor (PRB = 0) 820 2.80 GHz 805 2.
Electrical Specifications 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 775_VR_CONFIG_05A and 775_VR_CONFIG_05B refer to voltage regulator configurations that are defined in the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. Refer to Table 2-4 and Figure 2-1 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current.
Electrical Specifications Figure 2-1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A Pentium D Processor Icc [A] 0 10 20 30 40 50 60 70 80 90 100 VID - 0.000 VID - 0.013 VID - 0.025 Vcc Maximum VID - 0.038 VID - 0.050 VID - 0.063 Vcc [V] VID - 0.075 VID - 0.088 Vcc Typical VID - 0.100 VID - 0.113 VID - 0.125 Vcc Minimum VID - 0.138 VID - 0.150 VID - 0.163 VID - 0.175 VID - 0.188 NOTES: 1.
Electrical Specifications Table 2-5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor Icc (A) Voltage Deviation from VID Setting (V)1, 2, 3 Maximum Voltage 1.30 mΩ Typical Voltage 1.38 mΩ Minimum Voltage 1.45 mΩ 0 0.000 -0.019 -0.038 5 -0.007 -0.026 -0.045 10 -0.013 -0.033 -0.053 15 -0.020 -0.040 -0.060 20 -0.026 -0.047 -0.067 25 -0.033 -0.053 -0.074 30 -0.039 -0.060 -0.082 35 -0.046 -0.067 -0.089 40 -0.052 -0.074 -0.096 45 -0.059 -0.
Electrical Specifications Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_05B Pentium D Processor Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 VID - 0.000 VID - 0.025 Vcc Maximum VID - 0.050 VID - 0.075 Vcc [V] VID - 0.100 Vcc Typical VID - 0.125 VID - 0.150 Vcc Minimum VID - 0.175 VID - 0.200 VID - 0.
Electrical Specifications 2.5.3 VCC Overshoot Specification The Pentium D processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID).
Electrical Specifications 2.5.4 Die Voltage Validation Overshoot events on the processor must meet the specifications in Table 2-6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. Refer to the Voltage Regulator Down (VRD) 10.
Electrical Specifications Table 2-7. FSB Signal Groups Signal Group GTL+ Common Clock Input Signals1 Type Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#, AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, GTL+ Common Clock I/O Synchronous to BCLK[1:0] DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR# Signals GTL+ Source Synchronous I/O GTL+ Strobes Synchronous to assoc.
Electrical Specifications Table 2-8.
Electrical Specifications 2.6.3 FSB DC Specifications The processor front side bus DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. Table 2-10.
Electrical Specifications Table 2-12. PWRGOOD Input and TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1, VHYS Input Hysteresis 200 350 mV 3 V T+ Input low to high threshold voltage 0.5 * (VTT + VHYS_MIN) 0.5 * (VTT + VHYS_MAX) V 4 V T- Input high to low threshold voltage 0.5 * (VTT – VHYS_MAX) 0.
Electrical Specifications Table 2-14. VTTPWRGD DC Specifications Symbol Parameter Min Typ Max Unit VIL Input Low Voltage — — 0.3 V VIH Input High Voltage 0.9 — — V Notes Table 2-15. BOOTSELECT and MSID[1:0] DC Specifications Symbol Parameter Min Typ Max Unit Notes VIL Input Low Voltage — — 0.24 V 1 VIH Input High Voltage 0.96 — — V - NOTES: 1. 2.6.3.1 These parameters are not tested and are based on design simulations.
Electrical Specifications 2.7 Clock Specifications 2.7.1 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Pentium D processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The Pentium D processor uses a differential clocking implementation. Table 2-17.
Electrical Specifications Table 2-18. BSEL[2:0] Frequency Table for BCLK[1:0] 2.7.3 BSEL2 BSEL1 BSEL0 FSB Frequency L L L L RESERVED L H 133 MHz L H H RESERVED L H L 200 MHz H L L RESERVED H L H RESERVED H H H RESERVED H H L RESERVED Phase Lock Loop (PLL) and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators for the Pentium D processor. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter.
Electrical Specifications Figure 2-4. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB –0.5 dB Forbidden Zone Forbidden Zone –28 dB –34 dB DC 1 Hz fpeak Passband 1 MHz 66 MHz fcore High Frequency Band NOTES: 1. Diagram not to scale. 2. No specifications for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 4. fcore represents the maximum core frequency supported by the platform.
Package Mechanical Specifications 3 Package Mechanical Specifications The Intel® Pentium® D processor is packaged in a Flip-Chip Land Grid Array (FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications Figure 3-4.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The Pentium D processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the Pentium D processor is 22.03 g [0.78 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications Figure 3-6. Processor Top-Side Marking Example (Intel® Pentium® D Processor 805) Brand Processor Number/ S-Spec/ Country of Assy Frequency/L2 Cache/Bus/ 775_VR_CONFIG_05x FPO INTEL m © ‘04 XXXXXXXX 805 SLxxx [COO] 2.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-7 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 3-7.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the Intel® Pentium® D processor. The landout footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the landout arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 4-1.
Land Listing and Signal Descriptions Figure 4-2.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VCC AC27 VCC AC28 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 50 Land Name Land # Signal Buffer Type VCC AK14 VCC AK15 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 52 Land Name Land # Signal Buffer Type VSS AA24 VSS AA25 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VSS AJ23 VSS AJ24 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name 54 Land # Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VSS R30 VSS R5 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 56 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Datasheet Land # Land Name Signal Buffer Type C24 VSS C25 VTT C26 C27 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 58 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Datasheet Land # Land Name Signal Buffer Type J12 VCC Power/Other J13 VCC Power/Other J14 VCC J15 VCC J16 DP0# J17 DP3# J18 VCC J19 VCC J20 J21 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 60 Land Name Signal Buffer Type N30 VCC Power/Other P1 TESTHI11 Power/Other P2 SMI# P3 INIT# P4 VSS Power/Other P5 RESERVED Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Datasheet Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 62 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Datasheet Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 64 Land Name Signal Buffer Type AK2 VSS Power/Other AK3 ITP_CLK0 TAP Input AK4 VID4 Power/Other Output AK5 VSS Power/Other AK6 FORCEPR# Asynch GTL+ AK7 VSS Power/Other AK8 VCC AK9 VCC Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Datasheet Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 8) Name Type Description 236-byte A[35:3]# Input/ Output A[35:3]# (Address) define a physical memory address space. In subphase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins/lands of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/ lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 8) Name DRDY# Type Description Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 8) Name IERR# Type Output Description IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 8) Name Type Description MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: • Enabled or disabled. MCERR# Input/ Output • Asserted, if configured, for internal errors along with IERR#.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 8) Name RSP# SKTOCC# SMI# Type Input Output Input Description RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 8) Name Type Description TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents. TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic.
Land Listing and Signal Descriptions 74 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The Intel® Pentium® D processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations Refer to the Intel® Pentium® D Processor and Intel® Pentium® Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines and the Processor Power Characterization Methodology for the details of this methodology. The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time.
Thermal Specifications and Design Considerations Table 5-2. Thermal Profile for the Pentium D Processor with PRB=1 Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) 0 43.8 34 50.6 68 57.4 102 64.2 2 44.2 36 51.0 70 57.8 104 64.6 4 44.6 38 51.4 72 58.2 106 65.0 6 45.0 40 51.8 74 58.6 108 65.4 8 45.4 42 52.2 76 59.0 110 65.8 10 45.8 44 52.6 78 59.4 112 66.2 12 46.2 46 53.0 80 59.8 114 66.
Thermal Specifications and Design Considerations Table 5-3. Thermal Profile for the Pentium D Processor with PRB=0 Power (W) Maximum TC (°C) 0 Power Maximum TC (W) (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) 43.2 26 48.9 52 54.6 78 60.4 2 43.6 28 49.4 54 55.1 80 60.8 4 44.1 30 49.8 56 55.5 82 61.2 6 44.5 32 50.2 58 56.0 84 61.7 8 45.0 34 50.7 60 56.4 86 62.1 10 45.4 36 51.1 62 56.8 88 62.6 12 45.8 38 51.6 64 57.3 90 63.0 14 46.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) are specified in Table 5-1. These temperature specifications are meant to help ensure proper operation of the processor. Figure 5-3 illustrates where Intel recommends TC thermal measurements should be made.
Thermal Specifications and Design Considerations With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable.
Thermal Specifications and Design Considerations As a bi-directional signal, PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components.
Thermal Specifications and Design Considerations 5.2.5 THERMTRIP# Signal Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 4-3). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 4-3.
Thermal Specifications and Design Considerations Table 5-5.
Thermal Specifications and Design Considerations 84 Datasheet
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Intel® Pentium® D processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 6-1.
Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Enhanced HALT Powerdown State Enhanced HALT is a low power state entered when all logical processors have executed the HALT or MWAIT instructions and Enhanced HALT has been enabled via the BIOS.
Features 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop State and Enhanced HALT Snoop State. 6.2.4.
Boxed Processor Specifications 7 Boxed Processor Specifications The Intel® Pentium® D processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed Pentium D processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed Pentium D processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium D processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium D processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 7-4. Overall View Space Requirements for the Boxed Processor 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the Intel® Pentium® D Processor and Intel® Pentium® Processor Extreme Edition 840 Thermal and Mechanical Design Guidelines for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL. The boxed processor's fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it.
Boxed Processor Specifications Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 7-8.
Boxed Processor Specifications 7.3.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (For details on CONTROL, see Table 7-1) and remote thermal diode measurement capability the boxed processor will operate as follows: As processor power has increased the required thermal solutions have generated increasingly more noise.
Balanced Technology Extended (BTX) Type I Boxed Processor Specifications 8 Balanced Technology Extended (BTX) Type I Boxed Processor Specifications The Intel® Pentium® D processor will also be offered as an boxed Intel processor. Boxed Intel processors are intended for system integrators who build systems from largely standard components. The boxed Intel Pentium D processor will be supplied with a cooling solution known as the Thermal Module Assembly (TMA).
Balanced Technology Extended (BTX) Type I Boxed Processor Specifications 8.1 Mechanical Specifications 8.1.1 Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium D processor TMA. The boxed processor will be shipped with an unattached TMA. Figure 8-2 shows a mechanical representation of the boxed Pentium D processor TMA. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown. Figure 8-2.
Balanced Technology Extended (BTX) Type I Boxed Processor Specifications 8.1.3 Boxed Processor Support and Retention Module (SRM) The boxed processor TMA requires a SRM assembly to attach directly to the chassis base pan and to secure the processor and TMA in the mainboard socket. The boxed processor TMA will ship with the heatsink attach clip assembly, duct, and screws for attachment. The SRM must be supplied by the chassis hardware vendor.
Balanced Technology Extended (BTX) Type I Boxed Processor Specifications The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL. Note: The boxed processor’s fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it.
Balanced Technology Extended (BTX) Type I Boxed Processor Specifications Figure 8-5. Balanced Technology Extended (BTX) Mainboard Power Header Placement (hatched area) 8.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 8.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Balanced Technology Extended (BTX) Type I Boxed Processor Specifications 8.3.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header, it will operate as follows: The boxed processor fan will operate at different speeds over a short range of temperatures based on a thermistor located in the fan hub area. This allows the boxed processor fan to operate at a lower speed and noise level while thermistor temperatures are low.
Balanced Technology Extended (BTX) Type I Boxed Processor Specifications If the boxed processor TMA 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (see Table 8-1) and remote thermal diode measurement capability, the boxed processor will operate as described in the following paragraphs. As processor power has increased the required thermal solutions have generated increasingly more noise.
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Debug Tools Specifications 9 Debug Tools Specifications Refer to the eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms and the ITP700 Debug Port Design Guide for information regarding debug tools specifications. For more information, contact your Intel sales representative. The ITP700 Debug Port Design Guide is located at http://www.intel.com/design/xeon/guides/249679.htm. 9.
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