Datasheet

Module Connectors
August 2016 Intel® Joule™ Datasheet
Document number: 566641 rev. 1.0 Page 18
7.2 Module to expansion board connectors
7.2.1 Module electrostatic discharge
ESD testing is performed at the system level, where the module is connected to an expansion board, and not at the module
connectors. See the Intel® Joule™ expansion board design guide for more ESD information.
7.2.2 J6 connector interface signals
Table 8 J6 connector pin descriptions
Pin Signal Name Usage Description
36 +VDD1 Output System 1.8 V
30 +VDD3 Output System 3.3 V
41 +V5P0V_VCONN Input Power for USB3.0 CC pins for VCONN-powered accessory.
40 CHRG_INT_N Input General purpose input/output for the expansion board charger’s interrupt pin, active low.
Allows charger to interrupt host to report charger device status and faults.
Connected to GPIO_19.
35 CHRG_EN_N Output General purpose input/output for the expansion board charger’s enable pin, active low.
Allows battery to be charged when power is connected to VDC_IN.
Connected to GPIO_15.
43 CODEC_MCLK Output MCLK for Master Mode operation for I
2
S audio
16 ISH_I2C_0_SCL Output Integrated sensor hub port 0 I
2
C clock (open collector)
18 ISH_I2C_0_SDA Input/Output Integrated sensor hub port 0 I
2
C data (open collector)
21 ISH_I2C_1_SCL Output Integrated sensor hub port 1 I
2
C clock (open collector)
23 ISH_I2C_1_SDA Input/Output Integrated sensor hub port 1 I
2
C data (open collector)
46 HDMI_CLK_DN Output HDMI clock negative
44 HDMI_CLK_DP Output HDMI clock positive
68 DDI1_CTRL_CLK Output HDMI I2C clock
70 DDI1_CTRL_DAT Input/Output HDMI I2C data
62 HDMI_TX_0_DN Output HDMI data lane 0 negative
58 HDMI_TX_1_DN Output HDMI data lane 1 negative
50 HDMI_TX_2_DN Output HDMI data lane 2 negative
64 HDMI_TX_0_DP Output HDMI data lane 0 positive
56 HDMI_TX_1_DP Output HDMI data lane 1 positive
52 HDMI_TX_2_DP Output HDMI data lane 2 positive
74 UART2_CTS Input UART port 2 clear to send. UART port 2 is used as a debug port for BIOS messages during boot.
76 UART2_RTS Output UART port 2 ready to send. UART port 2 is used as a debug port for BIOS messages during boot.
80 UART2_RXD Input UART port 2 receive data. UART port 2 is used as a debug port for BIOS messages during boot.
78 UART2_TXD Output UART port 2 transmit data. UART port 2 is used as a debug port for BIOS messages during boot. Pin
includes hardware strapping functionality for DNX boot.
4,10,19,4
2,48,54,6
0,66,72,7
3,82,86,9
6,98,100
GND Ground System ground
39 I2S_1_CLK Input/Output I
2
S bit clock. Supplied by the module in master mode and serves as an input in slave mode.
45 I2S_1_FS Output I
2
S frame sync
47 I2S_1_RXD Input I
2
S receive data
49 I2S_1_TXD Output I
2
S transmit data
94 GPIO_22 Input/Output General purpose input/output
1 PWM_0 Output Programmable pulse width modulator port 0
3 PWM_1 Output Programmable pulse width modulator port 1