Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 99
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
2. Reset Types include: Power Button override, Intel ME initiated power button override, Intel ME initiated
host partition reset with power down, Intel ME Watchdog Timer, SMBus unconditional power down,
processor thermal trip, Intel® Xeon® Processor D-1500 Product Family catastrophic temperature event.
3. When the WAKE# pin is active and the PCI Express device is enabled to wake the system, Intel® Xeon®
Processor D-1500 Product Family will wake the platform.
4. SATA can only trigger a wake event in S1, but if PME is asserted prior to S4/S5 entry and software does not
clear the PME_B0_STS, a wake event would still result.
It is important to understand that the various GPIs have different levels of functionality
when used as wake events. The GPIs that reside in the core power well can only
generate wake events from sleep states where the core well is powered. Also, only
certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in
ACPI I/O space. Tab l e 3- 2 6 summarizes the use of GPIs as wake events.
The latency to exit the various Sleep states varies greatly and is heavily dependent on
power supply design, so much so that the exit latencies due to Intel® Xeon® Processor
D-1500 Product Family are insignificant.
3.12.6.4 PCI Express* WAKE# Signal and PME Event Message
PCI Express ports can wake the platform from any sleep state (S1, S4, or S5) using the
WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go
active in the GPE_STS register.
PCI Express ports have the ability to cause PME using messages. When a PME message
is received, Intel® Xeon® Processor D-1500 Product Family will set the PCI_EXP_STS
bit.
3.12.6.5 Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
The AFTERG3_EN bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). There are only three possible
events that will wake the system after a power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
(G3 state), the PWRBTN_STS bit is reset. When Intel® Xeon® Processor D-1500
Product Family exits G3 after power returns (RSMRST# goes high), the PWRBTN#
signal is already high (because V
CC
-standBy goes high before RSMRST# goes high)
and the PWRBTN_STS bit is 0.
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
Table 3-26. GPI Wake Events
GPI Power Well Wake From Notes
GPI[7:0] Core S1 ACPI Compliant
GPI[15:8] Suspend S1–S5 ACPI Compliant