Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 97
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.12.4.2 PCI Express* Hot-Plug
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI using the
GPE1 register. It is also capable of generating an SMI. However, it is not capable of
generating a wake event.
3.12.5 C-States
Intel® Xeon® Processor D-1500 Product Family-based systems implement C-states by
having the processor control the states. The chipset exchanges messages with the
processor as part of the C-state flow, but the chipset does not directly control any of
the processor impacts of C-states, such as voltage levels or processor clocking. In
addition to the messages, Intel® Xeon® Processor D-1500 Product Family also
provides additional information to the processor using a sideband pin (PMSYNCH). All of
the legacy C-state related pins (STPCLK#, STP_CPU#, DPRSLP#, DPRSLPVR#, and so
on) do not exist on Intel® Xeon® Processor D-1500 Product Family.
3.12.6 Sleep States
3.12.6.1 Sleep State Overview
Intel® Xeon® Processor D-1500 Product Family directly supports different sleep states
(S1–S5), which are entered by methods such as setting the SLP_EN bit or due to a
Power Button press. The entry to the Sleep states is based on several assumptions:
• The G3 state cannot be entered using any software mechanism. The G3 state
indicates a complete loss of power.
3.12.6.2 Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts
to gracefully put the system into the corresponding Sleep state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button
Override event. In this case the transition to the S5 state is less graceful, since
there are no dependencies on internal messages from the processing unit or on
clocks other than the RTC clock.
• Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can
occur when system is in S0 or S1 state.
• Shutdown by integrated manageability functions
• Internal watchdog timer time-out events
Table 3-24. Sleep Types
Sleep Type Comment
S1 System lowers the processor’s power consumption. No snooping is possible in this state.
S4 Intel® Xeon® Processor D-1500 Product Family asserts SLP_S3# and SLP_S4#. The
SLP_S4# signal shuts off the power to the memory subsystem. Only devices needed to wake
from this state should be powered.