Datasheet

Functional Description
94 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.12.4 SMI# / SCI Generation
Upon any enabled SMI event taking place while the End of SMI (EOS) bit is set, Intel®
Xeon® Processor D-1500 Product Family will clear the EOS bit and assert SMI to the
processor, which will cause it to enter SMM space. SMI assertion is performed using a
Virtual Legacy Wire (VLW) message. Prior system generations (those based upon
legacy processors) used an actual SMI# pin.
Once the SMI VLW has been delivered, Intel® Xeon® Processor D-1500 Product Family
takes no action on behalf of active SMI events until Host software sets the End of SMI
(EOS) bit. At that point, if any SMI events are still active, Intel® Xeon® Processor D-
1500 Product Family will send another SMI VLW message.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not (see Section 7.1.14). The interrupt remains asserted until all SCI
sources are removed.
Tab l e 3- 2 3 shows which events can cause an SMI and SCI. Some events can be
programmed to cause either an SMI or SCI. The usage of the event for SCI (instead of
SMI) is typically associated with an ACPI-based system. Each SMI or SCI source has a
corresponding enable and status bit.
Table 3-23. Causes of SMI and SCI (Sheet 1 of 3)
Cause SCI SMI Additional Enables Where Reported
PME# Yes Yes PME_EN=1 PME_STS
PME_B0 (Internal, Bus 0, PME-Capable
Agents)
Yes Yes PME_B0_EN=1 PME_B0_STS
PCI Express* PME Messages Yes Yes PCI_EXP_EN=1
(Not enabled for SMI)
PCI_EXP_STS
PCI Express Hot-Plug Message Yes Yes HOT_PLUG_EN=1
(Not enabled for SMI)
HOT_PLUG_STS
Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS
Power Button Override (Note 7) Yes No None PRBTNOR_STS
RTC Alarm Yes Yes RTC_EN=1 RTC_STS
Ring Indicate Yes Yes RI_EN=1 RI_STS
ACPI Timer overflow (2.34 sec.) Yes Yes TMROF_EN=1 TMROF_STS
Any GPI[15:0] Yes Yes GPI[x]_Route=10; GPI[x]_EN=1
(SCI)
GPI[x]_Route=01;
ALT_GPI[x]_SMI_EN=1 (SMI)
GPI[x]_STS
ALT_GPI[x]_SMI_STS
GPIO[27] Yes Yes GP27_EN=1 GP27_STS
TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS
GPIO[17] Yes Yes GPI[17] Route = 10
GP17_EN=1
(SCI);
GPI[17]_Route=01
ALT_GP17_SMI_EN=1
(SMI)
GP17_STS
ALT_GPI17_SMI_STS