Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 93
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Notes:
1. Some wake events can be preserved through power failure.
2. N/A
3. Includes all other applicable types of events that force the host into and stay in G2/S5.
4. If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4.
3.12.3 System Power Planes
The system has several independent power planes, as described in Tab l e 3-2 2 . When a
particular power plane is shut off, it should go to a 0 V level.
G2/S5 • Any Enabled Wake Event • G0/S0/C0
2
• Mechanical Off/Power Failure • G3
G2
•Any Enabled Wake Event
• Mechanical Off/Power Failure
•G0/S0/C0
2
• G1/S3, G1/S4 or G2/S5 (see Section 3.12.7)
•G3
G3
•Power Returns
• S0/C0 (reboot) or G2/S5
4
(stay off until power
button pressed or other wake event)
1,2
Table 3-21. State Transition Rules for Intel® Xeon® Processor D-1500 Product Family
(Sheet 2 of 2)
Present
State
Transition Trigger Next State
Table 3-22. System Power Plane
Plane Controlled By Description
Processor SLP_S3# signal The SLP_S3# signal can be used to cut the power to the processor
completely.
Main SLP_S3# signal When SLP_S3# goes active, power can be shut off to any circuit not
required to wake the system from the S3 state. Since the S3 state
requires that the memory context be preserved, power must be retained
to the main memory.
The processor, devices on the PCI bus, LPC I/F, and graphics will typically
be shut off when the Main power plane is off, although there may be small
subsections powered.
Memory SLP_S4# signal When SLP_S4# goes active, power can be shut off to any circuit not
required to wake the system from the S4. Since the memory context does
not need to be preserved in the S4 state, the power to the memory can
also be shut down.
Intel
®
ME SLP_A# This signal is asserted when the manageability platform goes to MOff.
Depending on the platform, this pin may be used to control the Intel
Management Engine power planes, LAN subsystem power, and the SPI
flash power.
LAN SLP_LAN# This signal is asserted in Sx/Moff when both host and Intel ME WoL are not
supported. This signal can be use to control power to the Intel GbE PHY.
Suspend
Well
SLP_SUS# This signal is asserted when the Sus rails can be externally shut off for
enhanced power saving.
DEVICE[n] Implementation
Specific
Individual subsystems may have their own power plane. For example,
GPIO signals may be used to control the power to disk drives, audio
amplifiers, or the display screen.