Datasheet

Functional Description
92 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.12.2 Intel® Xeon® Processor D-1500 Product Family and
System Power States
Tab l e 3- 2 0 shows the power states defined for INTEL® XEON® PROCESSOR D-1500
P
RODUCT FAMILY-based platforms. The state names generally match the corresponding
ACPI states.
Tab l e 3- 2 1 shows the transitions rules among the various states. Transitions among the
various states may appear to temporarily transition through intermediate states. For
example, in going from S0 to S3, it may appear to pass through the G1/S1 states.
These intermediate transitions and states are not listed in the table.
Table 3-20. General Power States for Systems Using Intel® Xeon® Processor D-1500
Product Family
State/
Substates
Legacy Name / Description
G0/S0/C0 Full On: Processor operating. Individual devices may be shut down or be placed into lower
power states to save power.
G0/S0/Cx Cx State: Cx states are processor power states within the S0 system state that provide for
various levels of power savings. The processor initiates C-state entry and exit while
interacting with Intel® Xeon® Processor D-1500 Product Family. Intel® Xeon® Processor D-
1500 Product Family will base its behavior on the processor state.
G1/S1 S1: Intel® Xeon® Processor D-1500 Product Family provides the S1 messages and the S0
messages on a wake event. It is preferred for systems to use C-states than S1.
G1/S3 Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is
shut off to non-critical circuits. Memory is retained and refreshes continue. All external
clocks stop except RTC.
G1/S4 Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is
then shut off to the system except for the logic required to resume.
G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic
required to restart. A full boot is required when waking.
G3 Mechanical OFF (MOFF): System context not maintained. All power is shut off except for
the RTC. No “Wake” events are possible. This state occurs if the user removes the main
system batteries , turns off a mechanical switch, or if the system power supply is at a level
that is insufficient to power the “waking” logic. When system power returns, transition will
depend on the state just prior to the entry to G3 and the AFTERG3_EN bit in the
GEN_PMCON_3 register (D31:F0, offset A4). Refer to Tab l e 3 - 2 7 for more details.
Table 3-21. State Transition Rules for Intel® Xeon® Processor D-1500 Product Family
(Sheet 1 of 2)
Present
State
Transition Trigger Next State
G0/S0/C0 • Internal Msg
•SLP_EN bit set
• Power Button Override
3
• Mechanical Off/Power Failure
•G0/S0/Cx
• G1/Sx or G2/S5 state
•G2/S5
•G3
G0/S0/Cx • Internal Msg
• Power Button Override
3
• Mechanical Off/Power Failure
•G0/S0/C0
•S5
•G3
G1/S1 or
G1/S3
• Any Enabled Wake Event
• Power Button Override
3
• Conditions met as described in
Section 3.12.7
• Mechanical Off/Power Failure
•G0/S0/C0
2
•G2/S5
•G3
G1/S4 • Any Enabled Wake Event • G0/S0/C0
2
• Power Button Override
3
•G2/S5
• Mechanical Off/Power Failure • G3