Datasheet

Functional Description
90 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.11.5 Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in a Intel® Xeon® Processor D-1500 Product Family-based
platform can be done by using a jumper on RTCRST# or GPI. Implementations should
not attempt to clear CMOS by using a jumper to pull VccRTC low.
Using RTCRST# to Clear CMOS
A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default,
the state of those configuration bits that reside in the RTC power well. When the
RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h Bit 2) will be set
and those configuration bits in the RTC power well will be set to their default state.
BIOS can monitor the state of this Bit, and manually clear the RTC CMOS array once
the system is booted.
The normal position would cause RTCRST# to be pulled up through a weak pull-up
resistor. Tab l e 3- 1 9 shows which bits are set to their default state when RTCRST# is
asserted. This RTCRST# jumper technique allows the jumper to be moved and then
replaced—all while
the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in
the
set state.
Table 3-19. Configuration Bits Reset by RTCRST# Assertion (Sheet 1 of 2)
Bit Name Register Location Bit(s)
Default
State
Alarm Interrupt Enable
(AIE)
Register B (General
Configuration) (RTC_REGB)
I/O space (RTC Index +
0Bh)
5X
Alarm Flag (AF) Register C (Flag Register)
(RTC_REGC)
I/O space (RTC Index +
0Ch)
5X
SWSMI_RATE_SEL General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 7:6 0
SLP_S4# Minimum
Assertion Width
General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 5:4 0
SLP_S4# Assertion
Stretch Enable
General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 3 0
RTC Power Status
(RTC_PWR_STS)
General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 2 0
Power Failure
(PWR_FLR)
General PM Configuration 3
Register (GEN_PMCON_3)
D31:F0:A4h 1 0
AFTERG3_EN General PM Configuration 3
Register GEN_PMCON_3
D31:F0:A4h 0 0
Power Button Override
Status
(PRBTNOR_STS)
Power Management 1 Status
Register (PM1_STS)
PMBase + 00h 11 0
RTC Event Enable
(RTC_EN)
Power Management 1 Enable
Register (PM1_EN)
PMBase + 02h 10 0
Sleep Type (SLP_TYP) Power Management 1 Control
(PM1_CNT)
PMBase + 04h 12:10 0
PME_EN General Purpose Event 0 Enables
Register (GPE0_EN)
PMBase + 2Ch 11 0
RI_EN General Purpose Event 0 Enables
Register (GPE0_EN)
PMBase + 2Ch 8 0