Datasheet

Intel® Xeon® Processor D-1500 Product Family 9
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.7.1 NMI_SC—NMI Status and Control Register......................................................282
7.7.2 NMI_EN—NMI Enable (and Real Time Clock Index) Register ..............................283
7.7.3 PORT92—Init Register..................................................................................283
7.7.4 COPROC_ERR—Coprocessor Error Register .....................................................283
7.7.5 RST_CNT—Reset Control Register..................................................................283
7.8 Power Management Registers ...................................................................................284
7.8.1 Power Management PCI Configuration Registers (PM—D31:F0)..........................284
7.8.2 APM I/O Decode Register .............................................................................292
7.8.3 Power Management I/O Registers..................................................................293
7.9 System Management TCO Registers ..........................................................................307
7.9.1 TCO_RLD—TCO Timer Reload and Current Value Register .................................307
7.9.2 TCO_DAT_IN—TCO Data In Register ..............................................................308
7.9.3 TCO_DAT_OUT—TCO Data Out Register .........................................................308
7.9.4 TCO1_STS—TCO1 Status Register .................................................................308
7.9.5 TCO2_STS—TCO2 Status Register .................................................................309
7.9.6 TCO1_CNT—TCO1 Control Register................................................................310
7.9.7 TCO2_CNT—TCO2 Control Register................................................................311
7.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ..............................................311
7.9.9 TCO_WDCNT—TCO Watchdog Control Register................................................312
7.9.10 SW_IRQ_GEN—Software IRQ Generation Register ...........................................312
7.9.11 TCO_TMR—TCO Timer Initial Value Register....................................................312
7.10 General Purpose I/O Registers ..................................................................................312
7.10.1 GPIO_USE_SEL—GPIO Use Select Register .....................................................313
7.10.2 GP_IO_SEL—GPIO Input/Output Select Register..............................................314
7.10.3 GP_LVL—GPIO Level for Input or Output Register ............................................314
7.10.4 GPO_BLINK—GPO Blink Enable Register .........................................................315
7.10.5 GP_SER_BLINK—GP Serial Blink Register........................................................316
7.10.6 GP_SB_CMDSTS—GP Serial Blink Command
Status Register ...........................................................................................316
7.10.7 GP_SB_DATA—GP Serial Blink Data Register...................................................317
7.10.8 GPI_NMI_EN—GPI NMI Enable Register..........................................................317
7.10.9 GPI_NMI_STS—GPI NMI Status Register.........................................................317
7.10.10 GPI_INV—GPIO Signal Invert Register ...........................................................318
7.10.11 GPIO_USE_SEL2—GPIO Use Select 2 Register.................................................318
7.10.12 GP_IO_SEL2—GPIO Input/Output Select 2 Register .........................................319
7.10.13 GP_LVL2—GPIO Level for Input or Output 2 Register........................................319
7.10.14 GPIO_USE_SEL3—GPIO Use Select 3 Register.................................................319
7.10.15 GP_IO_SEL3—GPIO Input/Output Select 3 Register .........................................320
7.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register........................................320
7.10.17 GP_RST_SEL1 — GPIO Reset Select Register ..................................................321
7.10.18 GP_RST_SEL2—GPIO Reset Select Register ....................................................321
7.10.19 GP_RST_SEL3—GPIO Reset Select Register ....................................................322
8 SATA Controller Registers (D31:F2)...............................................................................323
8.1 PCI Configuration Registers (SATA–D31:F2) ...............................................................323
8.1.1 VID—Vendor Identification Register (SATA—D31:F2) .......................................324
8.1.2 DID—Device Identification Register (SATA—D31:F2) ........................................324
8.1.3 PCICMD—PCI Command Register (SATA–D31:F2)............................................325
8.1.4 PCISTS — PCI Status Register (SATA–D31:F2)................................................325
8.1.5 RID—Revision Identification Register (SATA—D31:F2)......................................326
8.1.6 PI—Programming Interface Register (SATA–D31:F2)........................................326
8.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ...............................................327
8.1.8 BCC—Base Class Code Register (SATA–D31:F2SATA–D31:F2)...........................327
8.1.9 PMLT—Primary Master Latency Timer Register (SATA–D31:F2)..........................327
8.1.10 HTYPE—Header Type Register (SATA–D31:F2) ................................................327
8.1.11 PCMD_BAR—Primary Command Block Base Address Register (SATA–D31:F2)......328
8.1.12 PCNL_BAR—Primary Control Block Base Address Register (SATA–D31:F2) ..........328
8.1.13 SCMD_BAR—Secondary Command Block Base Address Register (SATA
D31:F2).....................................................................................................328
8.1.14 SCNL_BAR—Secondary Control Block Base Address Register (SATA D31:F2) ....... 328
8.1.15 BAR—Legacy Bus Master Base Address Register (SATA–D31:F2) .......................329
8.1.16 ABAR/SIDPBA1—AHCI Base Address Register / Serial ATA Index Data Pair
Base Address (SATA–D31:F2) .......................................................................329
8.1.17 SVID—Subsystem Vendor Identification Register (SATA–D31:F2) ......................330
8.1.18 SID—Subsystem Identification Register (SATA–D31:F2) ...................................330
8.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2)...........................................330
8.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) .............................................331