Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 89
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.11.1 Update Cycles
An update cycle occurs once a second, if the SET bit of register B is not asserted and
the divide chain is properly configured. During this procedure, the stored time and date
are incremented, overflow is checked, a matching alarm condition is checked, and the
time and date are rewritten to the RAM locations. The update cycle will start at least
488 µs after the UIP bit of register A is asserted, and the entire cycle does not take
more than 1984 µs to complete. The time and date RAM locations (0–9) are
disconnected from the external bus during this time.
To avoid update and data corruption conditions, external RAM access to these locations
can safely occur at two times. When a updated-ended interrupt is detected, almost
999 ms is available to read and write the valid time and date data. If the UIP bit of
Register A is detected to be low, there is at least 488 µs before the update cycle begins.
Warning: The overflow conditions for leap years adjustments are based on more than one date or
time item. To ensure proper operation when adjusting the time, the new time and data
values should be set at least two seconds before leap year occurs.
3.11.2 Interrupts
The real-time clock interrupt is internally routed within Intel® Xeon® Processor D-
1500 Product Family both to the I/O APIC and the 8259. It is mapped to interrupt
vector 8. This interrupt does not leave Intel® Xeon® Processor D-1500 Product Family,
nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored.
However, the High Performance Event Timers can also be mapped to IRQ8#; in this
case, the RTC interrupt is blocked.
3.11.3 Lockable RAM Ranges
The RTC battery-backed RAM supports two 8-byte ranges that can be locked using the
configuration space. If the locking bits are set, the corresponding range in the RAM will
not be readable or writable. A write cycle to those locations will have no effect. A read
cycle to those locations will not return the location’s actual value (resultant value
is undefined).
Once a range is locked, the range can be unlocked only by a hard reset, which will
invoke the BIOS and allow it to relock the RAM range.
3.11.4 Century Rollover
Intel® Xeon® Processor D-1500 Product Family detects a rollover when the Year byte
(RTC I/O space, index Offset 09h) transitions form 99 to 00. Upon detecting the
rollover, Intel® Xeon® Processor D-1500 Product Family sets the NEWCENTURY_STS
bit (TCOBASE + 04h, Bit 7). If the system is in an S0 state, this causes an SMI#. The
SMI# handler can update registers in the RTC RAM that are associated with century
value. If the system is in a sleep state (S1–S5) when the century rollover occurs,
Intel® Xeon® Processor D-1500 Product Family also sets the NEWCENTURY_STS bit,
but no SMI# is generated. When the system resumes from the sleep state, BIOS
should check the NEWCENTURY_STS bit and update the century value in the RTC RAM.