Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 85
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.9.3 PCI / PCI Express* Message-Based Interrupts
When external devices through PCI/PCI Express wish to generate an interrupt, they will
send the message defined in the PCI Express* Base Specification, Revision 2.0 for
generating INTA# – INTD#. These will be translated internal assertions/de-assertions
of INTA# – INTD#.
3.9.4 IOxAPIC Address Remapping
To support Intel Virtualization Technology, interrupt messages are required to go
through similar address remapping as any other memory request. Address remapping
allows for domain isolation for interrupts, so a device assigned in one domain is not
allowed to generate an interrupt to another domain.
The address remapping is based on the Bus: Device: Function field associated with the
requests. The internal APIC is required to initiate the interrupt message using a unique
Bus: Device: Function.
Intel® Xeon® Processor D-1500 Product Family allows BIOS to program the unique
Bus: Device: Function address for the internal APIC. This address field does not change
the APIC functionality and the APIC is not promoted as a stand-alone PCI device. See
Device 31: Function 0 Offset 6Ch for additional information.
3.9.5 External Interrupt Controller Support
Intel® Xeon® Processor D-1500 Product Family supports external APICs off of PCI
Express ports but does not support APICs on the PCI bus. The EOI special cycle is only
forwarded to PCI Express ports.
3.10 Serial Interrupt (D31:F0)
Intel® Xeon® Processor D-1500 Product Family supports a serial IRQ scheme. This
allows a single signal to be used to report interrupt requests. The signal used to
transmit this information is shared between Intel® Xeon® Processor D-1500 Product
Family and all participating peripherals. The signal line, SERIRQ, is synchronous to PCI
clock, and follows the sustained tri-state protocol that is used by all PCI signals. This
means that if a device has driven SERIRQ low, it will first drive it high synchronous to
PCI clock and release it the following PCI clock. The serial IRQ protocol defines this
sustained tri-state signaling in the following fashion:
• S – Sample Phase. Signal driven low
• R – Recovery Phase. Signal driven high
• T – Turn-around Phase. Signal released
Intel® Xeon® Processor D-1500 Product Family supports a message for 21 serial
interrupts. These represent the 15 ISA interrupts (IRQ0–1, 3–15), the four PCI
interrupts, and the control signals SMI# and IOCHK#. The serial IRQ protocol does not
support the additional APIC interrupts (20–23).
Note: When the SATA controller is configured for legacy IDE mode, IRQ14 and IRQ15 are
expected to behave as ISA legacy interrupts that cannot be shared (that is, through the
Serial Interrupt pin). If IRQ14 and IRQ15 are shared with Serial Interrupt pin then