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Functional Description

84 Intel® Xeon® Processor D-1500 Product Family

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

3.9.2 Interrupt Mapping

The I/O APIC within Intel® Xeon® Processor D-1500 Product Family supports 24 APIC

interrupts. Each interrupt has its own unique vector assigned by software. The interrupt

vectors are mapped as shown in the following table:

Notes:

1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15 receive

active-high internal interrupt sources, while interrupts 16 through 23 receive active-low internal interrupt

sources.

2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to

ensure the proper operation of HPET #2. Intel® Xeon® Processor D-1500 Product Family hardware does

not prevent sharing of IRQ 11.

3. If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other devices to

ensure the proper operation of HPET #3. Intel® Xeon® Processor D-1500 Product Family hardware does

not prevent sharing of IRQ 12.

4. PIRQ[E:H] are Multiplexed with GPIO pins. Interrupts PIRQ[E:H] will not be exposed if they are configured

as GPIOs.

Table 3-16. APIC Interrupt Mapping

IRQ #

Using

SERIRQ

Direct

from Pin

Using PCI

Message

Internal Modules

0 No No No Cascade from 8259 #1

1Yes No Yes

2 No No No 8254 Counter 0, HPET #0 (legacy mode)

3Yes No Yes

4Yes No Yes

5Yes No Yes

6Yes No Yes

7Yes No Yes

8No No NoRTC, HPET #1 (legacy mode)

9 Yes No Yes Option for SCI, TCO

10 Yes No Yes Option for SCI, TCO

11 Yes No Yes HPET #2, Option for SCI, TCO (Note 2)

12 Yes No Yes HPET #3 (Note 3)

13 No No No FERR# logic

14 Yes No Yes SATA Primary

(legacy mode)

15 Yes No Yes SATA

Secondary (legacy mode)

16 PIRQA# PIRQA# Yes Internal devices are routable; see Section 5.1.16

though Section 5.1.32.

17 PIRQB# PIRQB#

18 PIRQC# PIRQC#

19 PIRQD# PIRQD#

20 N/A PIRQE#4 Yes Option for SCI, TCO, HPET #0,1,2, 3. Other internal

devices are routable; see Section 5.1.16 though

Section 5.1.32.

21 N/A PIRQF#4

22 N/A PIRQG#4

23 N/A PIRQH#4