Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 83
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
requests. In the special mask mode, any interrupts may be selectively enabled by
loading the Mask Register with the appropriate pattern. The special mask mode is set
by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
3.8.6 Steering PCI Interrupts
Intel® Xeon® Processor D-1500 Product Family can be programmed to allow PIRQA#-
PIRQH# to be routed internally to interrupts 3–7, 9–12, 14 or 15. The assignment is
programmable through the PIRQx Route Control registers, located at 60–63h and 68–
6Bh in D31:F0. One or more PIRQx# lines can be routed to the same IRQx input. If
interrupt steering is not required, the Route registers can be programmed to
disable steering.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts
on a PCI board to share a single line across the connector. When a PIRQx# is routed to
specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
sensitive mode. Intel® Xeon® Processor D-1500 Product Family internally inverts the
PIRQx# line to send an active high level to the PIC. When a PCI interrupt is routed onto
the PIC, the selected IRQ can no longer be used by an active high device (through
SERIRQ). However, active low interrupts can share their interrupt with PCI interrupts.
Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external
PIRQ to be asserted. Intel® Xeon® Processor D-1500 Product Family receives the PIRQ
input, like all of the other external sources, and routes it accordingly.
3.9 Advanced Programmable Interrupt Controller
(APIC) (D31:F0)
In addition to the standard ISA-compatible PIC described in the previous section,
Intel® Xeon® Processor D-1500 Product Family incorporates the APIC. While the
standard interrupt controller is intended for use in a uni-processor system, APIC can be
used in either a uni-processor or multi-processor system.
3.9.1 Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through
memory writes on the normal data path to the processor, and interrupts are
handled without the need for the processor to run an interrupt acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 can be given a higher priority than
interrupt 3.
• More Interrupts. The I/O APIC in Intel® Xeon® Processor D-1500 Product Family
supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O
APIC devices in the system with their own interrupt vectors.