Datasheet

8 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
7.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F — D31:F0) ................................... 244
7.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F — D31:F0) ........................... 245
7.1.16 GC—GPIO Control Register (LPC I/F — D31:F0) .............................................. 245
7.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register (LPC I/F—D31:F0) ....... 246
7.1.18 SIRQ_CNTL—Serial IRQ Control Register (LPC I/F—D31:F0) ............................. 247
7.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register (LPC I/F—D31:F0) ....... 247
7.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function (LPC I/F—D31:F0) ............................ 248
7.1.21 LPC_HnBDF—HPET n Bus:Device:Function (LPC I/F—D31:F0) ........................... 248
7.1.22 LPC_I/O_DEC—I/O Decode Ranges Register (LPC I/F—D31:F0)......................... 249
7.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0) ...................................... 249
7.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register (LPC I/F—D31:F0) .......... 250
7.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register (LPC I/F—D31:F0) .......... 251
7.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register (LPC I/F—D31:F0) .......... 251
7.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register (LPC I/F—D31:F0) .......... 251
7.1.28 ULKMC—USB Legacy Keyboard / Mouse Control Register (LPC I/F—D31:F0) ....... 252
7.1.29 LGMR—LPC I/F Generic Memory Range Register (LPC I/F—D31:F0) ................... 253
7.1.30 BIOS_SEL1—BIOS Select 1 Register (LPC I/F—D31:F0) ................................... 253
7.1.31 BIOS_SEL2—BIOS Select 2 Register (LPC I/F—D31:F0) ................................... 254
7.1.32 BIOS_DEC_EN1—BIOS Decode Enable Register (LPC I/F—D31:F0) .................... 254
7.1.33 BIOS_CNTL—BIOS Control Register (LPC I/F—D31:F0) .................................... 256
7.1.34 FDCAP—Feature Detection Capability ID Register (LPC I/F—D31:F0).................. 257
7.1.35 FDLEN—Feature Detection Capability Length Register (LPC I/F—D31:F0)............ 257
7.1.36 FDVER—Feature Detection Version Register (LPC I/F—D31:F0) ......................... 257
7.1.37 FVECIDX—Feature Vector Index Register (LPC I/F—D31:F0) ............................. 257
7.1.38 FVECD—Feature Vector Data Register (LPC I/F—D31:F0) ................................. 258
7.1.39 Feature Vector Space .................................................................................. 258
7.1.40 RCBA—Root Complex Base Address Register (LPC I/F—D31:F0) ........................ 259
7.2 DMA I/O Registers .................................................................................................. 259
7.2.1 DMABASE_CA—DMA Base and Current Address Registers................................. 261
7.2.2 DMABASE_CC—DMA Base and Current Count Registers.................................... 261
7.2.3 DMAMEM_LP—DMA Memory Low Page Registers ............................................. 262
7.2.4 DMACMD—DMA Command Register............................................................... 262
7.2.5 DMASTA—DMA Status Register ..................................................................... 262
7.2.6 DMA_WRSMSK—DMA Write Single Mask Register ............................................ 263
7.2.7 DMACH_MODE—DMA Channel Mode Register.................................................. 263
7.2.8 DMA Clear Byte Pointer Register ................................................................... 264
7.2.9 DMA Master Clear Register........................................................................... 264
7.2.10 DMA_CLMSK—DMA Clear Mask Register......................................................... 264
7.2.11 DMA_WRMSK—DMA Write All Mask Register ................................................... 264
7.3 Timer I/O Registers ................................................................................................ 265
7.3.1 TCW—Timer Control Word Register ............................................................... 265
7.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register ................................. 267
7.3.3 Counter Access Ports Register ...................................................................... 268
7.4 8259 Interrupt Controller (PIC) Registers................................................................... 268
7.4.1 Interrupt Controller I/O MAP ........................................................................ 268
7.4.2 ICW1—Initialization Command Word 1 Register .............................................. 269
7.4.3 ICW2—Initialization Command Word 2 Register .............................................. 270
7.4.4 ICW3—Master Controller Initialization Command Word 3 Register...................... 270
7.4.5 ICW3—Slave Controller Initialization Command Word 3 Register ....................... 271
7.4.6 ICW4—Initialization Command Word 4 Register .............................................. 271
7.4.7 OCW1—Operational Control Word 1 (Interrupt Mask) Register .......................... 271
7.4.8 OCW2—Operational Control Word 2 Register .................................................. 272
7.4.9 OCW3—Operational Control Word 3 Register .................................................. 272
7.4.10 ELCR1—Master Controller Edge/Level Triggered Register.................................. 273
7.4.11 ELCR2—Slave Controller Edge/Level Triggered Register.................................... 273
7.5 Advanced Programmable Interrupt Controller (APIC) ................................................... 274
7.5.1 APIC Register Map ...................................................................................... 274
7.5.2 IND—Index Register.................................................................................... 275
7.5.3 DAT—Data Register..................................................................................... 275
7.5.4 EOIR—EOI Register..................................................................................... 275
7.5.5 ID—Identification Register ........................................................................... 276
7.5.6 VER—Version Register ................................................................................. 276
7.5.7 REDIR_TBL—Redirection Table Register ......................................................... 276
7.6 Real Time Clock Registers........................................................................................ 278
7.6.1 I/O Register Address Map ............................................................................ 278
7.6.2 Indexed Registers ....................................................................................... 279
7.7 Processor Interface Registers ................................................................................... 281