Datasheet

Functional Description
78 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.8.1 Interrupt Handling
3.8.1.1 Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending interrupts. Ta ble 3- 1 4 defines the IRR, ISR, and IMR.
3.8.1.2 Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle that is translated by the host
bridge into a PCI Interrupt Acknowledge Cycle to Intel® Xeon® Processor D-1500
Product Family. The PIC translates this command into two internal INTA# pulses
expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the
state of the interrupts for priority resolution. On the second INTA# pulse, the master or
slave sends the interrupt vector to the processor with the acknowledged interrupt code.
This code is based upon Bits 7:3 of the corresponding ICW2 register, combined with
three bits representing the interrupt within that controller.
3.8.1.3 Hardware/Software Interrupt Sequence
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.
3. The processor acknowledges the INTR and responds with an interrupt acknowledge
cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host
bridge. This command is broadcast over PCI by Intel® Xeon® Processor D-1500
Product Family.
4. Upon observing its own interrupt acknowledge cycle on PCI, Intel® Xeon®
Processor D-1500 Product Family converts it into the two cycles that the internal
8259 pair can respond to. Each cycle appears as an interrupt acknowledge pulse on
the internal INTA# pin of the cascaded interrupt controllers.
Table 3-14. Interrupt Status Registers
Bit Description
IRR Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge
mode, and by an active high level in level mode. This bit is set whether or not the interrupt is
masked. However, a masked interrupt will not generate INTR.
ISR Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an
interrupt acknowledge cycle is seen, and the vector returned is for that interrupt.
IMR Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts
will not generate INTR.
Table 3-15. Content of Interrupt Vector Byte
Master, Slave Interrupt Bits [7:3] Bits [2:0]
IRQ7,15 ICW2[7:3] 111
IRQ6,14 110
IRQ5,13 101
IRQ4,12 100
IRQ3,11 011
IRQ2,10 010
IRQ1,9 001
IRQ0,8 000