Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 73
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
When Intel® Xeon® Processor D-1500 Product Family sees one of these two
encodings, it ends the DMA transfer after this byte and de-asserts the DMA request to
the 8237. Therefore, if Intel® Xeon® Processor D-1500 Product Family indicated a 16-
bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC
value of 0000b or 1010b. Intel® Xeon® Processor D-1500 Product Family does not
attempt to transfer the second byte, and de-asserts the DMA request internally.
If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the
indicated size, then Intel® Xeon® Processor D-1500 Product Family only de-asserts
the DMA request to the 8237 since it does not need to end the transfer.
If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of
1001b (ready plus more data). This tells the 8237 that more data bytes are requested
after the current byte has been transferred, so Intel® Xeon® Processor D-1500
Product Family keeps the DMA request active to the 8237. Therefore, on an 8-bit
transfer size, if the peripheral indicates a SYNC value of 1001b to Intel® Xeon®
Processor D-1500 Product Family, the data will be transferred and the DMA request will
remain active to the 8237. At a later time, Intel® Xeon® Processor D-1500 Product
Family will then come back with another START–CYCTYPE–CHANNEL–SIZE and so on
combination to initiate another transfer to the peripheral.
The peripheral must not assume that the next START indication from Intel® Xeon®
Processor D-1500 Product Family is another grant to the peripheral if it had indicated a
SYNC value of 1001b. On a single mode DMA device, the 8237 will re-arbitrate after
every transfer. Only demand mode DMA devices can be assured that they will receive
the next START indication from Intel® Xeon® Processor D-1500 Product Family.
Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit
channel (first byte of a 16-bit transfer) is an error condition.
Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with
random data on DMA writes (peripheral to memory), and indicates to the 8237 that
the DMA transfer occurred, incrementing the 8237’s address and decrementing its
byte count.
3.6.7 SYNC Field / LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and
are ended through a SYNC field during the DMA transfer, the peripheral must obey the
following rule when initiating back-to-back transfers from a DMA channel.
The peripheral must not assert another message for eight LCLKs after a de-assertion is
indicated through the SYNC field. This is needed to allow the 8237, that typically runs
off a much slower internal clock, to see a message de-asserted before it is re-asserted
so that it can arbitrate to the next agent.
Under default operation, the host only performs 8-bit transfers on 8-bit channels and
16-bit transfers on 16-bit channels.
The method by which this communication between host and peripheral through system
BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC
peripheral are motherboard devices, no “plug-n-play” registry is required.