Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 71
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.6.2 Abandoning DMA Requests
DMA Requests can be de-asserted in two fashions: on error conditions by sending an
LDRQ# message with the ‘ACT’ bit cleared to 0, or normally through a SYNC field
during the DMA transfer. This section describes boundary conditions where the DMA
request needs to be removed prior to a data transfer.
There may be some special cases where the peripheral desires to abandon a DMA
transfer. The most likely case of this occurring is due to a floppy disk controller which
has overrun or underrun its FIFO, or software stopping a device prematurely.
In these cases, the peripheral wishes to stop further DMA activity. It may do so by
sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was
seen by Intel® Xeon® Processor D-1500 Product Family, there is no assurance that the
cycle has not been granted and will shortly run on LPC. Therefore, peripherals must
take into account that a DMA cycle may still occur. The peripheral can choose not to
respond to this cycle, in which case the host will abort it, or it can choose to complete
the cycle normally with any random data.
This method of DMA de-assertion should be prevented whenever possible, to limit
boundary conditions both on Intel® Xeon® Processor D-1500 Product Family and
the peripheral.
3.6.3 General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the
host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts
LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA
transfer is as follows:
1. Intel® Xeon® Processor D-1500 Product Family starts transfer by asserting 0000b
on LAD[3:0] with LFRAME# asserted.
2. Intel® Xeon® Processor D-1500 Product Family asserts ‘cycle type’ of DMA,
direction based on DMA transfer direction.
3. Intel® Xeon® Processor D-1500 Product Family asserts channel number and, if
applicable, terminal count.
4. Intel® Xeon® Processor D-1500 Product Family indicates the size of the transfer: 8
or 16 bits.
5. If a DMA reads…
— Intel® Xeon® Processor D-1500 Product Family drives the first 8 bits of data
and turns the bus around.
Figure 3-4. DMA Request Assertion through LDRQ#
Start MSB LSB ACT Start
LCLK
LDRQ#