Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 69
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.5.3 Summary of DMA Transfer Sizes
Ta b l e 3- 1 0 lists each of the DMA device transfer sizes. The column labeled “Current
Byte/Word Count Register” indicates that the register contents represents either the
number of bytes to transfer or the number of 16-bit words to transfer. The column
labeled “Current Address Increment/Decrement” indicates the number added to or
taken from the Current Address register after each DMA transfer cycle. The DMA
Channel Mode Register determines if the Current Address Register will be incremented
or decremented.
3.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words
Intel® Xeon® Processor D-1500 Product Family maintains compatibility with the
implementation of the DMA in the PC AT that used the 8237. The DMA shifts the
addresses for transfers to/from a 16-bit device count-by-words.
Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.
When programming the Current Address Register (when the DMA channel is in this
mode), the Current Address must be programmed to an even address with the address
value shifted right by one bit.
The address shifting is shown in Tab le 3-11 .
Note: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
3.5.4 Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as
an autoinitialize channel. When a channel undergoes autoinitialization, the original
values of the Current Page, Current Address and Current Byte/Word Count Registers
are automatically restored from the Base Page, Address, and Byte/Word Count
Registers of that channel following Terminal Count (TC). The Base Registers are loaded
simultaneously with the Current Registers by the microprocessor when the DMA
channel is programmed and remain unchanged throughout the DMA service. The mask
bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel
is ready to perform another DMA service, without processor intervention, as soon as a
valid DREQ is detected.
Table 3-10. DMA Transfer Size
DMA Device Date Size And Word Count
Current Byte/Word
Count Register
Current Address
Increment / Decrement
8-Bit I/O, Count By Bytes Bytes 1
16-Bit I/O, Count By Words (Address Shifted) Words 1
Table 3-11. Address Shifting in 16-Bit I/O DMA Transfers
Output
Address
8-Bit I/O Programmed Address
(Ch 0–3)
16-Bit I/O Programmed
Address (Ch 5–7)
(Shifted)
A0
A[16:1]
A[23:17]
A0
A[16:1]
A[23:17]
0
A[15:0]
A[23:17]