Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 67
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
Note: Intel® Xeon® Processor D-1500 Product Family cannot accept PCI write cycles from
PCI-to-PCI bridges or devices with similar characteristics (specifically those with a
“Retry Read” feature which is enabled) to an LPC device if there is an outstanding LPC
read cycle towards the same PCI device or bridge. These cycles are not part of normal
system operation, but may be encountered as part of platform validation testing using
custom test fixtures.
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of Intel® Xeon® Processor D-
1500 Product Family that supports two LPC bus masters, it drives 0010 for the START
field for grants to Bus Master 0 (requested using LDRQ0#) and 0011 for grants to Bus
Master 1 (requested using LDRQ1#.). Thus, no registers are needed to configure the
START fields for a particular bus master.
3.5 DMA Operation (D31:F0)
Intel® Xeon® Processor D-1500 Product Family supports LPC DMA using Intel® Xeon®
Processor D-1500 Product Family’s DMA controller. The DMA controller has registers
that are fixed in the lower 64 KB of I/O space. The DMA controller is configured using
registers in the PCI configuration space. These registers allow configuration of the
channels for use by LPC DMA.
The DMA circuitry incorporates the functionality of two 8237 DMA controllers with
seven independently programmable channels (Figure 3-3). DMA Controller 1 (DMA-1)
corresponds to DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to
Channels 5–7. DMA Channel 4 is used to cascade the two controllers and defaults to
cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for
any other purpose. In addition to accepting requests from DMA slaves, the DMA
controller also responds to requests that software initiates. Software may initiate a
DMA service request by setting any bit in the DMA Channel Request Register to a 1.
Floppy disk is not supported (or validated) in this Intel® Xeon® Processor D-1500
Product Family.
Each DMA channel is hardwired to the compatible settings for DMA device size:
Channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and Channels [7:5]
are hardwired to 16-bit, count-by-words (address shifted) transfers.
Intel® Xeon® Processor D-1500 Product Family provides 24-bit addressing in
compliance with the ISA-Compatible specification. Each channel includes a 16-bit ISA-
Compatible Current Register which holds the sixteen least-significant bits of the 24-bit
address, an ISA-Compatible Page Register which contains the eight next most
significant bits of address.
Figure 3-3. Intel® Xeon® Processor D-1500 Product Family DMA Controller
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
DMA-1
DMA-2