Datasheet

Functional Description
66 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
• A peripheral drives an invalid value.
3.4.1.9 I/O Cycles
For I/O cycles targeting registers specified in Intel® Xeon® Processor D-1500 Product
Family’s decode ranges, Intel® Xeon® Processor D-1500 Product Family performs I/O
cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are
8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, Intel® Xeon®
Processor D-1500 Product Family breaks the cycle up into multiple 8-bit transfers to
consecutive I/O addresses.
Note: If the cycle is not claimed by any peripheral (and subsequently aborted),
Intel® Xeon® Processor D-1500 Product Family returns a value of all 1s (FFh) to the
processor. This is to maintain compatibility with ISA I/O cycles where pull-up resistors
would keep the bus high if no device responds.
3.4.1.10 Bus Master Cycles
Intel® Xeon® Processor D-1500 Product Family supports Bus Master cycles and
requests (using LDRQ#) as defined in the Low Pin Count Interface Specification,
Revision 1.1. Intel® Xeon® Processor D-1500 Product Family has two LDRQ# inputs,
and thus supports two separate bus master devices. It uses the associated START fields
for Bus Master 0 (0010b) or Bus Master 1 (0011b).
Note: Intel® Xeon® Processor D-1500 Product Family does not support LPC Bus Masters
performing I/O cycles. LPC Bus Masters should only perform memory read or memory
write cycles.
3.4.1.11 LPC Power Management
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive
LDRQ# low or tri-state it. Intel® Xeon® Processor D-1500 Product Family shuts off the
LDRQ# input buffers. After driving SUS_STAT# active, Intel® Xeon® Processor D-1500
Product Family drives LFRAME# low, and tri-states (or drives low) LAD[3:0].
Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol
where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power
states which does not include asynchronous reset events. Intel® Xeon® Processor D-
1500 Product Family asserts both SUS_STAT# (connects to LPCPD#) and PLTRST#
(connects to LRST#) at the same time during a global reset. This is not inconsistent
with the LPC LPCPD# protocol.
3.4.1.12 Configuration and Intel® Xeon® Processor D-1500 Product Family
Implications
LPC I/F Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, Intel®
Xeon® Processor D-1500 Product Family includes several decoders. During
configuration, Intel® Xeon® Processor D-1500 Product Family must be programmed
with the same decode ranges as the peripheral. The decoders are programmed using
the D 31:F0 configuration space.