Datasheet

Functional Description
64 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.4.1.2 Start Field Definition
Note: All other encodings are RESERVED.
3.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)
Intel® Xeon® Processor D-1500 Product Family always drives Bit 0 of this field to 0.
Peripherals running bus master cycles must also drive Bit 0 to 0. Tab l e 3- 7 shows the
valid bit encodings.
3.4.1.4 Size
Bits[3:2] are reserved. Intel® Xeon® Processor D-1500 Product Family always drives
them to 00. Peripherals running bus master cycles are also supposed to drive 00 for
Bits 3:2; however, Intel® Xeon® Processor D-1500 Product Family ignores those bits.
Bits[1:0] are encoded as listed in Ta b l e 3-8 .
Table 3-6. Start Field Bit Definitions
Bits[3:0]
Encoding
Definition
0000 Start of cycle for a generic target
0010 Grant for bus master 0
0011 Grant for bus master 1
1111 Stop/Abort: End of a cycle for a target.
Table 3-7. Cycle Type Bit Definitions
Bits[3:2] Bit1 Definition
00 0 I/O Read
00 1 I/O Write
01 0 Memory Read
01 1 Memory Read
10 0 DMA Read
10 1 DMA Write
11 x Reserved. If a peripheral performing a bus master cycle generates this value,
Intel® Xeon® Processor D-1500 Product Family aborts the cycle.
Table 3-8. Transfer Size Bit Definition
Bits[1:0] Size
00 8-bit transfer (1 byte)
01 16-bit transfer (2 bytes)
10 Reserved. Intel® Xeon® Processor D-1500 Product Family never drives this combination. If
a peripheral running a bus master cycle drives this combination, Intel® Xeon® Processor D-
1500 Product Family may abort the transfer.
11 32-bit transfer (4 bytes)