Datasheet

Functional Description
Intel® Xeon® Processor D-1500 Product Family 63
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
3.4.1.1 LPC Cycle Types
Intel® Xeon® Processor D-1500 Product Family implements all of the cycle types
described in the Low Pin Count Interface Specification, Revision 1.1. Tab l e 3- 5 shows
the cycle types supported by Intel® Xeon® Processor D-1500 Product Family.
Notes:
1. Intel® Xeon® Processor D-1500 Product Family provides a single generic memory range (LGMR) for
decoding memory cycles and forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory
decode range is 64 KB in size and can be defined as being anywhere in the 4 GB memory space. This range
needs to be configured by BIOS during POST to provide the necessary memory resources. BIOS should
advertise the LPC Generic Memory Range as Reserved to the OS in order to avoid resource conflict. For
larger transfers, Intel® Xeon® Processor D-1500 Product Family performs multiple 8-bit transfers. If the
cycle is not claimed by any peripheral, it is subsequently aborted, and Intel® Xeon® Processor D-1500
Product Family returns a value of all 1s to the processor. This is done to maintain compatibility with ISA
memory cycles where pull-up resistors would keep the bus high if no device responds.
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any
address. However, the 2-byte transfer must be word-aligned (that is, with an address where A0=0). A
DWord transfer must be DWord-aligned (that is, with an address where A1 and A0 are both 0).
Figure 3-2. LPC Interface Diagram
Intel Xeon Processor D-1500
Product Family
LPC Device
SMI # ( Opti onal)
LDRQ[ 1: 0]# ( Opt ional)
LPCPD# (Optional)
LFRAME#
LAD[3:0]
33 MHz CLK
PL T_ R ST#
Table 3-5. LPC Cycle Types Supported
Cycle Type Comment
Memory Read 1 byte only. (See Note 1 below)
Memory Write 1 byte only. (See Note 1 below)
I/O Read 1 byte only. Intel® Xeon® Processor D-1500 Product Family breaks up 16-bit and
32-bit processor cycles into multiple 8-bit transfers.
I/O Write 1 byte only. Intel® Xeon® Processor D-1500 Product Family breaks up 16-bit and
32-bit processor cycles into multiple 8-bit transfers.
DMA Read Can be 1 or 2 bytes
DMA Write Can be 1 or 2 bytes
Bus Master Read Can be 1, 2 or 4 bytes. (See Note 2 below)
Bus Master Write Can be 1, 2 or 4 bytes. (See Note 2 below)