Datasheet

Functional Description
62 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
2. All subsequent requests targeting the function are not claimed and will be
master aborted immediately on the bus. This includes any configuration, I/O or
memory cycles. However, the function will continue to accept completions targeting
the function.
3.3.6.1.2 FLR Operation
Function resets all configuration, I/O, and memory registers of the function except
those indicated otherwise and resets all internal states of the function to the default or
initial condition.
3.3.6.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset completes. This bit can be
used to indicate to the software that the FLR reset completed.
Note: From the time the Initiate FLR bit is written to 1b, software must wait at least 100 ms
before accessing the function.
3.4 Low Pin Count (LPC) Bridge (with System and
Management Functions) (D31:F0)
The LPC bridge function of Intel® Xeon® Processor D-1500 Product Family resides in
PCI D31:F0. In addition to the LPC bridge function, D31:F0 contains other functional
units including DMA, Interrupt controllers, Timers, Power Management, System
Management, GPIO, and RTC. In this chapter, registers and functions associated with
other functional units (power management, GPIO, USB, and so on) are described in
their respective sections.
Note: The LPC bridge cannot be configured as a subtractive decode agent.
3.4.1 LPC Interface
Intel® Xeon® Processor D-1500 Product Family implements an LPC interface as
described in the Low Pin Count Interface Specification, Revision 1.1. The LPC interface
to Intel® Xeon® Processor D-1500 Product Family is shown in Figure 3-2. Intel®
Xeon® Processor D-1500 Product Family implements all of the signals that are shown
as optional, but peripherals are not required to do so.