Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 607
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.4.2.11 KTMSR—KT Modem Status Register (KT—D22:F3)
Address Offset: 06h Attribute: RO
Default Value: 00h Size: 8 bits
The functionality of the Modem is emulated by the FW. This register provides the status
of the current state of the control lines from the modem.
5 Transmit Holding Register Empty (THRE)— RO. This bit is always set when the mode (FIFO/
Non-FIFO) is changed by the Host. This bit is active only when the THR operation is enabled by the
FW. This bit has acts differently in the different modes:
Non FIFO: This bit is cleared by hardware when the Host writes to the THR registers and set by
hardware when the FW reads the THR register.
FIFO mode: This bit is set by hardware when the THR FIFO is empty, and cleared by hardware
when the THR FIFO is not empty.
This bit is reset on Host system reset or D3->D0 transition.
4 Break Interrupt (BI)— RO. This bit is cleared by hardware when the LSR register is being read
by the Host.
3:2 Reserved
1 Overrun Error (OE): This bit is cleared by hardware when the LSR register is being read by the
Host. The FW typically sets this bit, but it is cleared by hardware when the host reads the LSR.
0 Data Ready (DR)— RO.
Non-FIFO Mode: This bit is set when the FW writes to the RBR register and cleared by hardware
when the RBR register is being Read by the Host.
FIFO Mode: This bit is set by hardware when the RBR FIFO is not empty and cleared by hardware
when the RBR FIFO is empty.
This bit is reset on Host System Reset or D3->D0 transition.
Bit Description
Bit Description
7 Data Carrier Detect (DCD) — RO. In Loop Back mode this bit is connected by hardware to the
value of MCR bit 3.
6 Ring Indicator (RI) — RO. In Loop Back mode this bit is connected by hardware to the value of
MCR bit 2.
5 Data Set Ready (DSR) — RO. In Loop Back mode this bit is connected by hardware to the value
of MCR bit 0.
4 Clear To Send (CTS) — RO. In Loop Back mode this bit is connected by hardware to the value of
MCR bit 1.
3 Delta Data Carrier Detect (DDCD) — RO. This bit is set when bit 7 is changed. This bit is
cleared by hardware when the MSR register is being read by the HOST driver.
2 Trailing Edge of Read Detector (TERI) — RO. This bit is set when bit 6 is changed from 1 to 0.
This bit is cleared by hardware when the MSR register is being read by the Host driver.
1 Delta Data Set Ready (DDSR) — RO. This bit is set when bit 5 is changed. This bit is cleared by
hardware when the MSR register is being read by the Host driver.
0 Delta Clear To Send (DCTS) — RO. This bit is set when bit 4 is changed. This bit is cleared by
hardware when the MSR register is being read by the Host driver.