Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
606 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.4.2.8 KTLCR—KT Line Control Register (KT—D22:F3)
Address Offset: 03h Attribute: R/W
Default Value: 03h Size: 8 bits
The line control register specifies the format of the asynchronous data communications
exchange and sets the DLAB bit. Most bits in this register have no affect on hardware
and are only used by the FW.
17.4.2.9 KTMCR—KT Modem Control Register (KT—D22:F3)
Address Offset: 04h Attribute: R/W
Default Value: 00h Size: 8 bits
The Modem Control Register controls the interface with the modem. Since the FW
emulates the modem, the Host communicates to the FW using this register. Register
has impact on hardware when the Loopback mode is on.
17.4.2.10 KTLSR—KT Line Status Register (KT—D22:F3)
Address Offset: 05h Attribute: WO
Default Value: 00h Size: 8 bits
This register provides status information of the data transfer to the Host. Error
indication, etc. are provided by the HW/FW to the host using this register.
Bit Description
7 Divisor Latch Address Bit (DLAB)— R/W. This bit is set when the Host wants to read/write the
Divisor Latch LSB and MSB Registers. This bit is cleared when the Host wants to access the
Receive Buffer Register or the Transmit Holding Register or the Interrupt Enable Register.
6 Break Control (BC)— R/W. This bit has no affect on hardware.
5:4 Parity Bit Mode (PBM)— R/W. This bit has no affect on hardware.
3 Parity Enable (PE)— R/W.This bit has no affect on hardware.
2 Stop Bit Select (SBS)— R/W. This bit has no affect on hardware.
1:0 Word Select Byte (WSB)— R/W. This bit has no affect on hardware.
Bit Description
7:5 Reserved
4 Loop Back Mode (LBM)— R/W. When set by the Host, this bit indicates that the serial port is in
loop Back mode. This means that the data that is transmitted by the host should be received.
Helps in debug of the interface.
3 Output 2 (OUT2)— R/W. This bit has no affect on hardware in normal mode. In loop back mode
the value of this bit is written by hardware to the Modem Status Register bit 7.
2 Output 1 (OUT1)— R/W. This bit has no affect on hardware in normal mode. In loop back mode
the value of this bit is written by hardware to Modem Status Register bit 6.
1 Request to Send Out (RTSO)— R/W. This bit has no affect on hardware in normal mode. In
loopback mode, the value of this bit is written by hardware to Modem Status Register bit 4.
0 Data Terminal Ready Out (DRTO)— R/W. This bit has no affect on hardware in normal mode. In
loopback mode, the value in this bit is written by hardware to Modem Status Register Bit 5.
Bit Description
7 RX FIFO Error (RXFER)— RO. This bit is cleared in non FIFO mode. This bit is connected to BI bit
in FIFO mode.
6 Transmit Shift Register Empty (TEMT)— RO. This bit is connected by HW to bit 5 (THRE) of
this register.