Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
604 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
THR:
When host wants to transmit data in the non-FIFO mode, it writes to this register. In
FIFO mode, writes by host to this address cause the data byte to be written by
hardware to Intel ME memory (THR FIFO).
17.4.2.3 KTDLLR—KT Divisor Latch LSB Register (KT—D22:F3)
Address Offset: 00h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the KT DLL register. Host can Read/Write to this register only
when the DLAB bit (KTLCR[7]) is 1. When this bit is 0, Host accesses the KTTHR or the
KTRBR depending on Read or Write.
This is the standard Serial Port Divisor Latch register. This register is only for software
compatibility and does not affect performance of the hardware.
17.4.2.4 KTIER—KT Interrupt Enable Register (KT—D22:F3)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This implements the KT Interrupt Enable register. Host access to this address, depends
on the state of the DLAB bit (KTLCR[7]). It must be “0” to access this register. The bits
enable specific events to interrupt the Host.
17.4.2.5 KTDLMR—KT Divisor Latch MSB Register (KT—D22:F3)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this
bit is 0, Host accesses the KTIER.
This is the standard Serial interface's Divisor Latch register's MSB. This register is only
for SW compatibility and does not affect performance of the hardware.
Bit Description
7:0 Transmit Holding Register (THR)— WO. Implements the Transmit Data register of the Serial
Interface. If the Host does a write, it writes to the Transmit Holding Register.
Bit Description
7:0 Divisor Latch LSB (DLL)— R/W. Implements the DLL register of the Serial Interface.
Bit Description
7:4 Reserved
3 MSR (IER2)— R/W. When set, this bit enables bits in the Modem Status register to cause an
interrupt to the host.
2 LSR (IER1)— R/W.When set, this bit enables bits in the Receiver Line Status Register to cause an
Interrupt to the Host.
1 THR (IER1)— R/W. When set, this bit enables an interrupt to be sent to the Host when the
transmit Holding register is empty.
0 DR (IER0)— R/W. When set, the Received Data Ready (or Receive FIFO Timeout) interrupts are
enabled to be sent to Host.