Datasheet
Intel® Management Engine Subsystem Registers (D22:F[3:0])
602 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.4.1.16 MID—Message Signaled Interrupt Capability ID Register (KT—D22:F3)
Address Offset: D0–D1h Attribute: RO
Default Value: 0005h Size: 16 bits
Message Signaled Interrupt is a feature that allows the device/function to generate an
interrupt to the host by performing a DWORD memory write to a system specified
address with system specified data. This register is used to identify and configure an
MSI capable device.
17.4.1.17 MC—Message Signaled Interrupt Message Control Register (KT—
D22:F3)
Address Offset: D2–D3h Attribute: RO, R/W
Default Value: 0080h Size: 16 bits
17.4.1.18 MA—Message Signaled Interrupt Message Address Register (KT—
D22:F3)
Address Offset: D4–D7h Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
This register specifies the DWORD aligned address programmed by system software for
sending MSI.
17.4.1.19 MAU—Message Signaled Interrupt Message Upper Address Register
(KT—D22:F3)
Address Offset: D8–DBh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Bit Description
15:8 Next Pointer (NEXT)— RO. This value indicates this is the last item in the list.
7:0 Capability ID (CID)— RO. This field value of Capabilities ID indicates device is capable of
generating MSI.
Bit Description
15:8 Reserved
7 64-Bit Address Capable (C64)— RO. Capable of generating 64-bit and 32-bit messages.
6:4 Multiple Message Enable (MME)— R/W.These bits are R/W for software compatibility, but only
one message is ever sent by the PT function.
3:1 Multiple Message Capable (MMC)— RO. Only one message is required.
0 MSI Enable (MSIE)— R/W. If set, MSI is enabled and traditional interrupt pins are not used to
generate interrupts.
Bit Description
31:2 Address (ADDR)— R/W. Lower 32 bits of the system specified message address, always DWord
aligned.
1:0 Reserved
Bit Description
31:4 Reserved
3:0 Address (ADDR)— R/W. Upper 4 bits of the system specified message address.