Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 601
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.4.1.12 CAP—Capabilities Pointer Register (KT—D22:F3)
Address Offset: 34h Attribute: RO
Default Value: C8h Size: 8 bits
This optional register is used to point to a linked list of new capabilities implemented by
the device.
17.4.1.13 INTR—Interrupt Information Register (KT—D22:F3)
Address Offset: 3C–3Dh Attribute: R/W, RO
Default Value: 0200h Size: 16 bits
17.4.1.14 PID—PCI Power Management Capability ID Register (KT—D22:F3)
Address Offset: C8–C9h Attribute: RO
Default Value: D001h Size: 16 bits
17.4.1.15 PC—PCI Power Management Capabilities ID Register (KT—D22:F3)
Address Offset: CA–CBh Attribute: RO
Default Value: 0023h Size: 16 bits
Bit Description
7:0 Capability Pointer (CP)— RO. This field indicates that the first capability pointer is offset C8h
(the power management capability).
Bit Description
15:8 Interrupt Pin (IPIN)— RO. A value of 1h/2h/3h/4h indicates that this function implements
legacy interrupt on INTA/INTB/INTC/INTD, respectively
FunctionValueINTx
(3 KT/Serial Port)02hINTB
7:0 Interrupt Line (ILINE)— R/W. The value written in this register tells which input of the system
interrupt controller, the device's interrupt pin is connected to. This value is used by the OS and the
device driver, and has no affect on the hardware.
Bit Description
15:8 Next Capability (NEXT)— RO. A value of D0h points to the MSI capability.
7:0 Cap ID (CID)— RO. This field indicates that this pointer is a PCI power management.
Bit Description
15:11 PME Support (PME)— RO.This field indicates no PME# in the PT function.
10:6 Reserved
5 Device Specific Initialization (DSI)— RO. This bit indicates that no device-specific initialization
is required.
4 Reserved
3 PME Clock (PMEC)— RO. This bit indicates that PCI clock is not required to generate PME#
2:0 Version (VS)— RO. This field indicates support for the PCI Power Management Specification,
Revision 1.2.