Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 599
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.4.1.3 CMD—Command Register (KT—D22:F3)
Address Offset: 04–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
17.4.1.4 STS—Device Status Register (KT—D22:F3)
Address Offset: 06–07h Attribute: RO
Default Value: 00B0h Size: 16 bits
17.4.1.5 RID—Revision ID Register (KT—D22:F3)
Address Offset: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
17.4.1.6 CC—Class Codes Register (KT—D22:F3)
Address Offset: 09–0Bh Attribute: RO
Default Value: 070002h Size: 24 bits
Bit Description
15:11 Reserved
10 Interrupt Disable (ID)— R/W. This bit disables pin-based INTx# interrupts. This bit has no
effect on MSI operation.
1 = Internal INTx# messages will not be generated.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled.
9:3 Reserved
2 Bus Master Enable (BME)— R/W. This bit controls the KT function's ability to act as a master for
data transfers. This bit does not impact the generation of completions for split transaction
commands. For KT, the only bus mastering activity is MSI generation.
1 Memory Space Enable (MSE)— R/W. This bit controls Access to the PT function's target
memory space.
0 I/O Space enable (IOSE)— R/W. This bit controls access to the PT function's target I/O space.
Bit Description
15:11 Reserved
10:9 DEVSEL# Timing Status (DEVT)— RO. This field controls the device select time for the PT
function's PCI interface.
8:5 Reserved
4 Capabilities List (CL)— RO. This bit indicates that there is a capabilities pointer implemented in
the device.
3 Interrupt Status (IS)— RO. This bit reflects the state of the interrupt in the function. Setting of
the Interrupt Disable bit to 1 has no affect on this bit. Only when this bit is a 1 and ID bit is 0 is the
INTB interrupt asserted to the Host.
2:0 Reserved
Bit Description
7:0 Revision ID — RO. See the Specification Update for the value of the RID Register.
Bit Description
23:16 Base Class Code (BCC)—RO This field indicates the base class code of the KT host controller
device.
15:8 Sub Class Code (SCC)—RO This field indicates the sub class code of the KT host controller
device.
7:0 Programming Interface (PI)—RO This field indicates the programming interface of the KT host
controller device.