Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 597
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.4.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor Table Pointer
Byte 0 Register (IDER—D22:F2)
Address Offset: 0Ch Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor Table Pointer
Byte 1 Register (IDER—D22:F2)
Address Offset: 0Dh Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor Table Pointer
Byte 2 Register (IDER—D22:F2)
Address Offset: 0Eh Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.16 IDESBMDTPR3—IDE Secondary Bus Master Descriptor Table Pointer
Byte 3 Register (IDER—D22:F2)
Address Offset: 0Fh Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:0 Descriptor Table Pointer Byte 0 (DTPB0) — R/W. This register implements the Byte 0 (1 of 4
bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the
secondary channel. This register is read/write by the HOST interface.
Bit Description
7:0 Descriptor Table Pointer Byte 1 (DTPB1) — R/W. This register implements the Byte 1 (of four
bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the
secondary channel. This register is programmed by the Host.
Bit Description
7:0 Descriptor Table Pointer Byte 2 (DTPB2) — R/W. This register implements the Byte 2 (of four
bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the
secondary channel. This register is programmed by the Host.
Bit Description
7:0 Descriptor Table Pointer Byte 3 (DTPB3) — R/W. This register implements the Byte 3 (of four
bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the
secondary channel. This register is programmed by the Host.