Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
596 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.4.9 IDESBMCR—IDE Secondary Bus Master Command Register (IDER—
D22:F2)
Address Offset: 08h Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.10 IDESBMDS0R—IDE Secondary Bus Master Device Specific 0 Register
(IDER—D22:F2)
Address Offset: 09h Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.11 IDESBMSR—IDE Secondary Bus Master Status Register (IDER—
D22:F2)
Address Offset: 0Ah Attribute: R/W, RO
Default Value: 80h Size: 8 bits
17.3.4.12 IDESBMDS1R—IDE Secondary Bus Master Device Specific 1 Register
(IDER—D22:F2)
Address Offset: 0Bh Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:4 Reserved
3 Read Write Command (RWC) — R/W. This bit sets the direction of bus master transfer. When 0,
Reads are performed from system memory; when 1, writes are performed to System Memory.
This bit should not be changed when the bus master function is active.
2:1 Reserved
0 Start/Stop Bus Master (SSBM) — R/W. This bit gates the bus master operation of IDE function
when zero.
Writing 1 enables the bus master operation. Bus master operation can be halted by writing a 0 to
this bit. Operation cannot be stopped and resumed.
This bit is cleared after data transfer is complete as indicated by either the BMIA bit or the INT bit
of the Bus Master status register is set or both are set.
Bit Description
7:0 Device Specific Data0 (DSD0) — R/W. This register implements the bus master Device Specific
1 register of the secondary channel. This register is programmed by the Host.
Bit Description
7 Simplex Only (SO) — R/W. This bit indicates whether both Bus Master Channels can be operated
at the same time or not.
0 = Both can be operated independently
1 = Only one can be operated at a time.
6 Drive 1 DMA Capable (D1DC) — R/W. This bit is read/write by the host.
5 Drive 0 DMA Capable (D0DC) — R/W. This bit is read/write by the host.
4:0 Reserved
Bit Description
7:0 Device Specific Data1 (DSD1) — R/W. This register implements the bus master Device Specific
1 register of the secondary channel. This register is programmed by the Host for device specific
data if any.