Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 595
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.4.4 IDEPBMDS1R—IDE Primary Bus Master Device Specific 1 Register
(IDER—D22:F2)
Address Offset: 03h Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor Table Pointer Byte
0 Register (IDER—D22:F2)
Address Offset: 04h Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor Table Pointer Byte
1 Register (IDER—D22:F2)
Address Offset: 05h Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor Table Pointer Byte
2 Register (IDER—D22:F2)
Address Offset: 06h Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor Table Pointer Byte
3 Register (IDER—D22:F2)
Address Offset: 07h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:0 Device Specific Data1 (DSD1) — R/W. Device Specific Data.
Bit Description
7:0 Descriptor Table Pointer Byte 0 (DTPB0) — R/W. This register implements the Byte 0 (1 of 4
bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the
primary channel. This register is read/write by the HOST interface.
Bit Description
7:0 Descriptor Table Pointer Byte 1 (DTPB1) — R/W. This register implements the Byte 1 (of four
bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the
primary channel. This register is programmed by the Host.
Bit Description
7:0 Descriptor Table Pointer Byte 2 (DTPB2) — R/W. This register implements the Byte 2 (of four
bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the
primary channel. This register is programmed by the Host.
Bit Description
7:0 Descriptor Table Pointer Byte 3 (DTPB3) — R/W. This register implements the Byte 3 (of four
bytes) of the descriptor table Pointer (four I/O byte addresses) for bus master operation of the
primary channel. This register is programmed by the Host.