Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
594 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.4.1 IDEPBMCR—IDE Primary Bus Master Command Register (IDER—
D22:F2)
Address Offset: 00h Attribute: RO, R/W
Default Value: 00h Size: 8 bits
This register implements the bus master command register of the primary channel.
This register is programmed by the Host.
17.3.4.2 IDEPBMDS0R—IDE Primary Bus Master Device Specific 0 Register
(IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
17.3.4.3 IDEPBMSR—IDE Primary Bus Master Status Register (IDER—D22:F2)
Address Offset: 02h Attribute: RO, R/W
Default Value: 80h Size: 8 bits
Bit Description
7:4 Reserved
3 Read Write Command (RWC) — R/W. This bit sets the direction of bus master transfer.
0 = Reads are performed from system memory
1 = Writes are performed to System Memory.
This bit should not be changed when the bus master function is active.
2:1 Reserved
0 Start/Stop Bus Master (SSBM) — R/W. This bit gates the bus master operation of IDE function
when 0. Writing 1 enables the bus master operation. Bus master operation can be halted by
writing a 0 to this bit. Operation cannot be stopped and resumed.
This bit is cleared after data transfer is complete as indicated by either the BMIA bit or the INT bit
of the Bus Master status register is set or both are set.
Bit Description
7:0 Device Specific Data0 (DSD0) — R/W. Device Specific
Bit Description
7 Simplex Only (SO) — RO. Value indicates whether both Bus Master Channels can be operated at
the same time or not.
0 = Both can be operated independently
1 = Only one can be operated at a time.
6 Drive 1 DMA Capable (D1DC) — R/W. This bit is read/write by the host (not write 1 clear).
5 Drive 0 DMA Capable (D0DC) — R/W. This bit is read/write by the host (not write 1 clear).
4:3 Reserved
2 Interrupt (INT) — R/W. This bit is set by the hardware when it detects a positive transition in the
interrupt logic (refer to IDE host interrupt generation diagram).The hardware will clear this bit
when the Host SW writes 1 to it.
1 Error (ER) — R/W. Bit is typically set by FW. Hardware will clear this bit when the Host SW writes
1 to it.
0 Bus Master IDE Active (BMIA) — RO. This bit is set by hardware when SSBM register is set to 1
by the Host. When the bus master operation ends (for the whole command) this bit is cleared by
firmware. This bit is not cleared when the HOST writes 1 to it.