Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 593
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.3.2 IDASR—IDE Alternate Status Register (IDER—D22:F2)
Address Offset: 2h Attribute: RO
Default Value: 00h Size: 8 bits
This register implements the Alternate Status register of the Control block of the IDE
function. This register is a mirror register to the status register in the command block.
Reading this register by the HOST does not clear the IDE interrupt of the DEV selected
device
Host read of this register when DEV=0 (Master), Host gets the mirrored data of
IDESD0R register.
Host read of this register when DEV=1 (Slave), host gets the mirrored data of IDESD1R
register.
17.3.4 IDER BAR4 Registers
Bit Description
7:0 IDE Alternate Status Register (IDEASR)— RO. This field mirrors the value of the DEV0/ DEV1
status register, depending on the state of the DEV bit on Host reads.
Table 17-8. IDER BAR4 Register Address Map
Address
Offset
Register Symbol Register Name
Default
Value
Attribute
0h IDEPBMCR IDE Primary Bus Master Command Register 00h RO, R/W
1h IDEPBMDS0R IDE Primary Bus Master Device Specific 0
Register
00h R/W
2h IDEPBMSR IDE Primary Bus Master Status Register 80h RO, R/W
3h IDEPBMDS1R IDE Primary Bus Master Device Specific 1
Register
00h R/W
4h IDEPBMDTPR0 IDE Primary Bus Master Descriptor Table
Pointer Register Byte 0
00h R/W
5h IDEPBMDTPR1 IDE Primary Bus Master Descriptor Table
Pointer Register Byte 1
00h R/W
6h IDEPBMDTPR2 IDE Primary Bus Master Descriptor Table
Pointer Register Byte 2
00h R/W
7h IDEPBMDTPR3 IDE Primary Bus Master Descriptor Table
Pointer Register Byte 3
00h R/W
8h IDESBMCR IDE Secondary Bus Master Command
Register
00h RO, R/W
9h IDESBMDS0R IDE Secondary Bus Master Device Specific 0
Register
00h R/W
Ah IDESBMSR IDE Secondary Bus Master Status Register 00h R/W, RO
Bh IDESBMDS1R IDE Secondary Bus Master Device Specific 1
Register
00h R/W
Ch IDESBMDTPR0 IDE Secondary Bus Master Descriptor Table
Pointer Register Byte 0
00h R/W
Dh IDESBMDTPR1 IDE Secondary Bus Master Descriptor Table
Pointer Register Byte 1
00h R/W
Eh IDESBMDTPR2 IDE Secondary Bus Master Descriptor Table
Pointer Register Byte 2
00h R/W
Fh IDESBMDTPR3 IDE Secondary Bus Master Descriptor Table
Pointer Register Byte 3
00h R/W