Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
592 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.2.22 IDECR—IDE Command Register (IDER—D22:F2)
Address Offset: 07h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Command register of the command block of the IDE
function. This register can be written only by the Host.
When the HOST reads the same address it reads the Status register DEV0 if DEV=0 or
Status Register DEV1 if DEV=1 (Drive/Head register bit [4]).
17.3.3 IDER BAR1 Registers
17.3.3.1 IDDCR—IDE Device Control Register (IDER—D22:F2)
Address Offset: 2h Attribute: WO
Default Value: 00h Size: 8 bits
This register implements the Device Control register of the Control block of the IDE
function. This register is Write only by the Host.
When the HOST reads to the same address it reads the Alternate Status register.
1 Index (IDX) — R/W. This bit is set once per rotation of the medium when the index mark passes
under the read/write head.
0 Error (ERR) — R/W. When set, this bit indicates an error occurred in the process of executing the
previous command. The Error Register of the selected device contains the error information
Bit Description
Bit Description
7:0 IDE Command Data (IDECD) — R/W. Host sends the commands (read/ write, etc.) to the drive
using this register.
Table 17-7. IDER BAR1 Register Address Map
Address
Offset
Register
Symbol
Register Name
Default
Value
Attribute
2h IDDCR IDE Device Control Register 00h RO, WO
2h IDASR IDE Alternate status Register 00h RO
Bit Description
7:3 Reserved
2 Software reset (S_RST) — WO. When this bit is set by the Host, it forces a reset to the device.
1 Host interrupt Disable (nIEN) — WO. When set, this bit disables hardware from sending
interrupt to the Host.
0 Reserved