Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
590 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.2.17 IDEDHIR—IDE Drive/Head In Register (IDER—D22:F2)
Address Offset: 06h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Drive/Head register of the command block of the IDE.
This register can be written only by the Host. When host writes to this register, all 3
registers (IDEDHIR, IDEDHOR0, IDEDHOR1) are updated with the written value.
Host read to this register address reads the IDE Drive/Head Out Register (IDEDHOR0)
if DEV=0 or IDEDHOR1 if DEV=1.
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to '1') in addition to Host system reset and D3->D0
transition of the function.
17.3.2.18 IDDHOR1—IDE Drive Head Out Register Device 1 Register (IDER—
D22:F2)
Address Offset: 06h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read only by the Host. Host read to this Drive/head In register address
reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=1
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to '1') in addition to the Host system reset and D3
to D0 transition of the IDE function.
When the host writes to this address, it updates the value of the IDEDHIR register.
17.3.2.19 IDDHOR0—IDE Drive Head Out Register Device 0 Register (IDER—
D22:F2)
Address Offset: 06h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read only by the Host. Host read to this Drive/head In register address
reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=0.
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to 1) in addition to the Host system reset and D3 to
D0 transition of the IDE function.
When the host writes to this address, it updates the value of the IDEDHIR register.
Bit Description
7:0 IDE Cylinder High Data (IDECHD) — R/W. Cylinder High data register for IDE command block.
Bit Description
7:0 IDE Drive/Head Data (IDEDHD) — R/W. Register defines the drive number, head number and
addressing mode.
Bit Description
7:0 IDE Drive Head Out DEV 1 (IDEDHO1) — R/W. Drive/Head Out register of Slave device.