Datasheet

Functional Description

Intel® Xeon® Processor D-1500 Product Family 59

Datasheet - Volume 1 of 4: Integrated Platform Controller Hub

March 2015

Both mechanisms use an internal logic signal to wake the system up. The wake-up

steps are as follows:

1. Host wake event occurs (packet is not delivered to host).

2. The Platform LAN Connect Device receives a WoL packet/link status change.

3. The Platform LAN Connect Device sends a wake indication to Intel® Xeon®

Processor D-1500 Product Family (this requires the WAKELAN_N pin from the

Intel® Ethernet Network Connection I127LM/V Platform LAN Connect Device to be

connected to Intel® Xeon® Processor D-1500 Product Family GPIO27 pin.

4. The Platform LAN Connect Device wakes up the integrated GbE controller using an

SMBus message on SMLink.

5. The integrated GbE controller sets the PME_STATUS bit.

6. System wakes from Sx state to S0 state.

7. The host LAN function is transitioned to D0.

8. The host clears the PME_STATUS bit.

3.3.4.1.1 Advanced Power Management Wake Up

Advanced Power Management Wake Up or APM Wake Up was previously known as

Wake on LAN (WoL). It is a feature that has existed in the 10/100 Mb/s NICs for several

generations. The basic premise is to receive a broadcast or unicast packet with an

explicit data pattern and then to assert a signal to wake up the system. In earlier

generations, this was accomplished by using a special signal that ran across a cable to

a defined connector on the motherboard. The NIC would assert the signal for

approximately 50 ms to signal a wake up. The integrated GbE controller uses (if

configured to) an in-band PM_PME message for this.

At power up, the integrated GbE controller reads the APM Enable bits from the NVM PCI

Init Control Word into the APM Enable (APME) bits of the Wake Up Control (WUC)

When APM wake up is enabled, the integrated GbE controller checks all incoming

packets for Magic Packets.

Once the integrated GbE controller receives a matching Magic Packet, it:

• Sets the Magic Packet Received bit in the Wake Up Status (WUS) register.

• Sets the PME_Status bit in the Power Management Control/Status Register

(PMCSR).

APM wake up is supported in all power states and only disabled if a subsequent NVM

read results in the APM Wake Up bit being cleared or the software explicitly writes a 0b

to the APM Wake Up (APM) bit of the WUC register.

Note: APM wake up settings will be restored to NVM default by Intel® Xeon® Processor D-

1500 Product Family when LAN connected Device (PHY) power is turned off and

subsequently restored. Some example host WoL flows are:

• When system transitions to G3 after WoL is disabled from the BIOS, APM host WoL

would get enabled.

• Anytime power to the LAN Connected Device (PHY) is cycled while in S4/S5 after

WoL is disabled from the BIOS, APM host WoL would get enabled. Anytime power to

the LAN Connected Device (PHY) is cycled while in S3, APM host WoL configuration

is lost.