Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
586 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.2.2 IDEERD1—IDE Error Register DEV1 (IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Error register of the command block of the IDE function.
This register is read only by the HOST interface when DEV = 1 (slave device).
17.3.2.3 IDEERD0—IDE Error Register DEV0 (IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Error register of the command block of the IDE function.
This register is read only by the HOST interface when DEV = 0 (master device).
17.3.2.4 IDEFR—IDE Features Register (IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Feature register of the command block of the IDE
function. This register can be written only by the Host.
When the HOST reads the same address, it reads the Error register of Device 0 or
Device 1 depending on the device_select bit (bit 4 of the drive/head register).
17.3.2.5 IDESCIR—IDE Sector Count In Register (IDER—D22:F2)
Address Offset: 02h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Sector Count register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDESCIR, IDESCOR0, IDESCOR1) are updated with the written
value.
A host read to this register address reads the IDE Sector Count Out Register IDESCOR0
if DEV=0 or IDESCOR1 if DEV=1
Bit Description
7:0 IDE Error Data (IDEED) — R/W. Drive reflects its error/ diagnostic code to the host using this
register at different times.
Bit Description
7:0 IDE Error Data (IDEED)— R/W. Drive reflects its error/ diagnostic code to the host using this
register at different times.
Bit Description
7:0 IDE Feature Data (IDEFD) — R/W. IDE drive specific data written by the Host
Bit Description
7:0 IDE Sector Count Data (IDESCD)— R/W. Host writes the number of sectors to be read or
written.