Datasheet
Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 585
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.2 IDER BAR0 Registers
17.3.2.1 IDEDATA—IDE Data Register (IDER—D22:F2)
Address Offset: 0h Attribute: R/W
Default Value: 00h Size: 8 bits
The IDE data interface is a special interface that is implemented in the HW. This data
interface is mapped to IO space from the host and takes read and write cycles from the
host targeting master or slave device.
Writes from host to this register result in the data being written to Intel ME memory.
Reads from host to this register result in the data being fetched from Intel ME memory.
Data is typically written/ read in WORDs. Intel SPS FW must enable hardware to allow
it to accept Host initiated Read/ Write cycles, else the cycles are dropped.
Table 17-6. IDER BAR0 Register Address Map
Address
Offset
Register
Symbol
Register Name
Default
Value
Attribute
0h IDEDATA IDE Data Register 00h R/W
1h IDEERD1 IDE Error Register DEV1 00h R/W
1h IDEERD0 IDE Error Register DEV0 00h R/W
1h IDEFR IDE Features Register 00h R/W
2h IDESCIR IDE Sector Count In Register 00h R/W
2h IDESCOR1 IDE Sector Count Out Register Device 1 00h R/W
2h IDESCOR0 IDE Sector Count Out Register Device 0 00h R/W
3h IDESNOR0 IDE Sector Number Out Register Device 0 00h R/W
3h IDESNOR1 IDE Sector Number Out Register Device 1 00h R/W
3h IDESNIR IDE Sector Number In Register 00h R/W
4h IDECLIR IDE Cylinder Low In Register 00h R/W
4h IDCLOR1 IDE Cylinder Low Out Register Device 1 00h R/W
4h IDCLOR0 IDE Cylinder Low Out Register Device 0 00h R/W
5h IDCHOR0 IDE Cylinder High Out Register Device 0 00h R/W
5h IDCHOR1 IDE Cylinder High Out Register Device 1 00h R/W
5h IDECHIR IDE Cylinder High In Register 00h R/W
6h IDEDHIR IDE Drive/Head In Register 00h R/W
6h IDDHOR1 IDE Drive Head Out Register Device 1 00h R/W
6h IDDHOR0 IDE Drive Head Out Register Device 0 00h R/W
7h IDESD0R IDE Status Device 0 Register 80h R/W
7h IDESD1R IDE Status Device 1 Register 80h R/W
7h IDECR IDE Command Register 00h R/W
Bit Description
7:0 IDE Data Register (IDEDR) — R/W. Data Register implements the data interface for IDE. All
writes and reads to this register translate into one or more corresponding write/reads to Intel ME
memory.