Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
584 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.1.21 MC—Message Signaled Interrupt Message Control Register (IDER—
D22:F2)
Address Offset: D2–D3h Attribute: RO, R/W
Default Value: 0080h Size: 16 bits
17.3.1.22 MA—Message Signaled Interrupt Message Address Register (IDER—
D22:F2)
Address Offset: D4–D7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
17.3.1.23 MAU—Message Signaled Interrupt Message Upper Address Register
(IDER—D22:F2)
Address Offset: D8–DBh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
17.3.1.24 MD—Message Signaled Interrupt Message Data Register (IDER—
D22:F2)
Address Offset: DC–DDh Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:8 Reserved
7 64-Bit Address Capable (C64) — RO. Capable of generating 64-bit and 32-bit messages.
6:4 Multiple Message Enable (MME) — R/W. These bits are R/W for software compatibility, but only
one message is ever sent by the PT function.
3:1 Multiple Message Capable (MMC) — RO. Only one message is required.
0 MSI Enable (MSIE) — R/W. If set, MSI is enabled and traditional interrupt pins are not used to
generate interrupts.
Bit Description
31:2 Address (ADDR) — R/W. This field contains the Lower 32 bits of the system specified message
address, always DWord aligned
1:0 Reserved
Bit Description
31:4 Reserved
3:0 Address (ADDR) — R/W. This field contains the Upper 4 bits of the system specified message
address.
Bit Description
15:0 Data (DATA) — R/W. This content is driven onto the lower word of the data bus of the MSI
memory write transaction.