Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 583
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.1.18 PC—PCI Power Management Capabilities Register (IDER—D22:F2)
Address Offset: CA–CBh Attribute: RO
Default Value: 0023h Size: 16 bits
17.3.1.19 PMCS—PCI Power Management Control and Status Register (IDER—
D22:F2)
Address Offset: CC-CFh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
17.3.1.20 MID—Message Signaled Interrupt Capability ID Register (IDER—
D22:F2)
Address Offset: D0–D1h Attribute: RO
Default Value: 0005h Size: 16 bits
Bit Description
15:11 PME_Support (PSUP) — RO. This five-bit field indicates the power states in which the function
may assert PME#. IDER can assert PME# from any D-state except D1 or D2 which are not
supported by IDER.
10:9 Reserved
8:6 Aux_Current (AC) — RO. Reports the maximum Suspend well current required when in the
D3
cold
state. Value of 000b is reported.
5 Device Specific Initialization (DSI) — RO. Indicates whether device-specific initialization is
required.
4 Reserved
3 PME Clock (PMEC) — RO. Indicates that PCI clock is not required to generate PME#.
2:0 Version (VS) — RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI Power
Management Specification.
Bit Description
31:4 Reserved
3 No Soft Reset (NSR) — RO.
0 = Devices do perform an internal reset upon transitioning from D3hot to D0 using software
control of the PowerState bits. Configuration Context is lost when performing the soft reset.
Upon transition from the D3hot to the D0 state, full re-initialization sequence is needed to
return the device to D0 Initialized.
1 = Devices do not perform an internal reset upon transitioning from D3hot to D0. Configuration
Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional
operating system intervention is required to preserve Configuration Context beyond writing
the PowerState bits.
2 Reserved
1:0 Power State (PS)— R/W. This field is used both to determine the current power state of the PT
function and to set a new power state. The values are:
00 = D0 state
11 = D3
HOT
state
When in the D3
HOT
state, the controller's configuration space is available, but the I/O and memory
spaces are not. Additionally, interrupts are blocked. If software attempts to write a '10' or '01' to
these bits, the write will be ignored.
Bit Description
15:8 Next Pointer (NEXT) — RO. This value indicates this is the last item in the capabilities list.
7:0 Capability ID (CID) — RO. The Capabilities ID value indicates device is capable of generating an
MSI.