Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 581
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.1.9 PCTLBA—Primary Control Block Base Address Register (IDER—
D22:F2)
Address Offset: 14–17h Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
17.3.1.10 SCMDBA—Secondary Command Block Base Address Register (IDER—
D22:F2)
Address Offset: 18–1Bh Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
17.3.1.11 SCTLBA—Secondary Control Block Base Address Register (IDER—
D22:F2)
Address Offset: 1C–1Fh Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
17.3.1.12 LBAR—Legacy Bus Master Base Address Register (IDER—D22:F2)
Address Offset: 20–23h Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
15:2 Base Address (BAR)—R/W. Base Address of the BAR1 I/O space (4 consecutive I/O locations)
1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space
Bit Description
31:16 Reserved
15:3 Base Address (BAR)—R/W. Base Address of the I/O space (8 consecutive I/O locations).
2:1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.
Bit Description
31:16 Reserved
15:2 Base Address (BAR)—R/W. Base Address of the I/O space (4 consecutive I/O locations).
1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.
Bit Description
31:16 Reserved
15:4 Base Address (BA)—R/W. Base Address of the I/O space (16 consecutive I/O locations).
3:1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.