Datasheet

Intel® Management Engine Subsystem Registers (D22:F[3:0])
580 Intel® Xeon® Processor D-1500 Product Family
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.1.5 RID—Revision Identification Register (IDER—D22:F2)
Address Offset: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
17.3.1.6 CC—Class Codes Register (IDER—D22:F2)
Address Offset: 09–0Bh Attribute: RO
Default Value: 010185h Size: 24 bits
17.3.1.7 CLS—Cache Line Size Register (IDER—D22:F2)
Address Offset: 0Ch Attribute: RO
Default Value: 00h Size: 8 bits
17.3.1.8 PCMDBA—Primary Command Block IO Bar Register (IDER—D22:F2)
Address Offset: 10–13h Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
4 Capabilities List (CL)—RO. This bit indicates that there is a capabilities pointer implemented in
the device.
3 Interrupt Status (IS)—RO. This bit reflects the state of the interrupt in the function. Setting of
the Interrupt Disable bit to 1 has no affect on this bit. Only when this bit is a 1 and ID bit is 0 is the
INTc interrupt asserted to the Host.
2:0 Reserved
Bit Description
Bit Description
7:0 Revision ID — RO. See the Specification Update for the value of the RID Register.
Bit Description
23:16 Base Class Code (BCC)—RO This field indicates the base class code of the IDER host controller
device.
15:8 Sub Class Code (SCC)—RO This field indicates the sub class code of the IDER host controller
device.
7:0 Programming Interface (PI)—RO This field indicates the programming interface of the IDER
host controller device.
Bit Description
7:0 Cache Line Size (CLS)—RO. All writes to system memory are Memory Writes.
Bit Description
31:16 Reserved
15:3 Base Address (BAR)—R/W Base Address of the BAR0 I/O space (8 consecutive I/O locations).
2:1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.