Datasheet
Intel® Management Engine Subsystem Registers (D22:F[3:0])
Intel® Xeon® Processor D-1500 Product Family 579
Datasheet - Volume 1 of 4: Integrated Platform Controller Hub
March 2015
17.3.1.1 VID—Vendor Identification Register (IDER—D22:F2)
Address Offset: 00–01h Attribute: RO
Default Value: 8086h Size: 16 bits
17.3.1.2 DID—Device Identification Register (IDER—D22:F2)
Address Offset: 02–03h Attribute: RO
Default Value: See bit description Size: 16 bits
17.3.1.3 PCICMD— PCI Command Register (IDER—D22:F2)
Address Offset: 04–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
17.3.1.4 PCISTS—PCI Device Status Register (IDER—D22:F2)
Address Offset: 06–07h Attribute: RO
Default Value: 00B0h Size: 16 bits
D4h–D7h MA Message Signaled Interrupt
Message Address
00000000h R/W, RO
D8h–DBh MAU Message Signaled Interrupt
Message Upper Address
00000000h RO, R/W
DC–DDh MD Message Signaled Interrupt
Message Data
0000h R/W
Table 17-5. IDE Redirect Function IDER Register Address Map (Sheet 2 of 2)
Address
Offset
Register
Symbol
Register Name Default Value Attribute
Bit Description
15:0 Vendor ID (VID) — RO. This is a 16-bit value assigned by Intel.
Bit Description
15:0 Device ID (DID) — RO. This is a 16-bit value assigned to the Intel® Xeon® Processor D-1500
Product Family IDER controller. See the Specification Update for the value of the DID Register.
Bit Description
15:11 Reserved
10 Interrupt Disable (ID)—R/W. This disables pin-based INTx# interrupts. This bit has no effect on
MSI operation. When set, internal INTx# messages will not be generated. When cleared, internal
INTx# messages are generated if there is an interrupt and MSI is not enabled.
9:3 Reserved
2 Bus Master Enable (BME)—RO. This bit controls the PT function's ability to act as a master for
data transfers. This bit does not impact the generation of completions for split transaction
commands.
1 Memory Space Enable (MSE)—RO. PT function does not contain target memory space.
0 I/O Space enable (IOSE)—RO. This bit controls access to the PT function's target I/O space.
Bit Description
15:11 Reserved
10:9 DEVSEL# Timing Status (DEVT)—RO. This bit controls the device select time for the PT
function's PCI interface.
8:5 Reserved